Paper

Research

Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI

Abstract Ara is a highly scalable and energy-efficient 64-bit vector processor based on the RISC-V vector extension (v0.5 draft), realized in 22 nm FD-SOI technology. Its lane-based microarchitecture achieves clock speeds exceeding

By Admin 2 Jun 2019 • 2 min read •

Research

Fast TLB Simulation for RISC-V Systems (Full Report)

By Admin 16 May 2019 • 3 min read •

Research

Fast TLB Simulation for RISC-V Systems

Abstract This paper introduces a novel, fast TLB simulation framework specifically designed for exploring Translation Lookaside Buffer (TLB) behaviors in multi-core RISC-V systems. Integrated into the QEMU dynamic binary translated emulator, the framework

By Admin 16 May 2019 • 2 min read •

Research

The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology (Full Report)

By Admin 10 Apr 2019 • 3 min read •

Research

The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology

Abstract This paper presents a thorough energy and performance analysis of Ariane, an open-source, single-issue 64-bit RISC-V core implemented for application-class processing and supporting the Linux OS. Taped-out in 22nm FDSOI technology, the

By Admin 10 Apr 2019 • 2 min read •

Research

NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22nm FD-SOI (Full Report)

By Admin 1 Dec 2018 • 3 min read •

Research

NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22nm FD-SOI

Abstract NTX is an energy-efficient streaming accelerator designed for 32-bit floating-point generalized reduction workloads, including training large Deep Neural Networks. Implemented in 22nm FD-SOI technology and orchestrated by a RISC-V core, the accelerator

By Admin 1 Dec 2018 • 2 min read •

Research

JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores (Full Report)

By Admin 20 Nov 2018 • 3 min read •

Research

JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores

Abstract JuxtaPiton is introduced as the first open-source, general-purpose, heterogeneous-ISA processor designed to enable crucial energy efficiency research. It integrates a small RISC-V core alongside a modified OpenSPARC T1 core within the OpenPiton

By Admin 20 Nov 2018 • 1 min read •

Research

Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator (Full Report)

By Admin 5 Nov 2018 • 3 min read •

Research

Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator

Abstract This paper details the formal verification of WARP-V, an open-source RISC-V core generator developed using the timing-abstract, transaction-level TL-Verilog methodology. The verification employed the established riscv-formal framework, investigating the synergy between transaction-level

By Admin 5 Nov 2018 • 1 min read •

Research

CIDPro: Custom Instructions for Dynamic Program Diversification (Full Report)

By Admin 4 Sep 2018 • 3 min read •