Paper

Research

Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core

Abstract This paper addresses the prevention of microarchitectural covert channels that exploit shared hardware resources to leak information across OS security boundaries, focusing on the open-source 64-bit RISC-V Ariane core. Initial attempts using

By Admin 1 May 2020 • 2 min read •

Research

Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters (Full Report)

By Admin 14 Apr 2020 • 3 min read •

Research

Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters

Abstract This paper proposes a light-weight Hardware-Accelerated Synchronization and Communication Unit (SCU) designed for shared-L1-memory multiprocessor clusters operating under energy-efficient near-threshold computing (NTC) conditions. Integrated into an eight-core RISC-V cluster, the SCU significantly

By Admin 14 Apr 2020 • 2 min read •

Research

Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem (Full Report)

By Admin 11 Mar 2020 • 3 min read •

Research

Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem

Abstract This paper presents a cycle-accurate evaluation framework for software-hardware co-design solutions targeting decimal computation within the RISC-V ecosystem. The methodology involves integrating dedicated hardware, realized as an accelerator supporting new decimal-oriented instructions,

By Admin 11 Mar 2020 • 1 min read •

Research

A portable and Linux capable RISC-V computer system in Verilog HDL (Full Report)

By Admin 10 Feb 2020 • 3 min read •

Research

A portable and Linux capable RISC-V computer system in Verilog HDL

Abstract This paper introduces a novel, portable RISC-V computer system implemented entirely in Verilog HDL, explicitly designed to boot the Linux operating system. Addressing the scarcity of public, Linux-capable RISC-V systems, the proposed

By Admin 10 Feb 2020 • 1 min read •

Research

RVCoreP : An optimized RISC-V soft processor of five-stage pipelining (Full Report)

By Admin 10 Feb 2020 • 3 min read •

Research

RVCoreP : An optimized RISC-V soft processor of five-stage pipelining

Abstract RVCoreP is an optimized five-stage pipelined soft processor designed for FPGAs, implementing the RISC-V 32-bit Integer (RV32I) instruction set architecture. The processor incorporates three key optimization techniques focusing on instruction fetch/branch

By Admin 10 Feb 2020 • 1 min read •

Research

SSR: A Stall Scheme Reducing Bubbles in Load-Use Hazard of RISC-V Pipeline (Full Report)

By Admin 23 Dec 2019 • 3 min read •

Research

SSR: A Stall Scheme Reducing Bubbles in Load-Use Hazard of RISC-V Pipeline

Abstract This paper introduces SSR (Stall Scheme Reducing bubbles), a microarchitectural modification designed to reduce performance degradation caused by load-use hazards in RISC-V pipelines. The proposed method replaces the traditional ID-EXE stage stall

By Admin 23 Dec 2019 • 2 min read •

Research

Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores (Full Report)

By Admin 19 Nov 2019 • 3 min read •