Paper

Research

Composite Enclaves: Towards Disaggregated Trusted Execution

Abstract Trusted Execution Environments (TEEs) traditionally fail to protect code leveraging specialized or disaggregated heterogeneous hardware outside the main CPU, due to their fixed hardware Trusted Computing Base (TCB). This paper proposes "

By Admin 20 Oct 2020 • 2 min read •

Research

A RISC-V SystemC-TLM simulator (Full Report)

By Admin 20 Oct 2020 • 3 min read •

Research

A RISC-V SystemC-TLM simulator

Abstract This work presents a SystemC-TLM based simulator for a RISC-V microcontroller, prioritizing simplicity and expandability for System-on-Chip (SoC) development. It integrates a full RISC-V Instruction Set Simulator (ISS) supporting key ISA extensions,

By Admin 20 Oct 2020 • 2 min read •

Research

Elasticlave: An Efficient Memory Model for Enclaves (Full Report)

By Admin 16 Oct 2020 • 3 min read •

Research

Elasticlave: An Efficient Memory Model for Enclaves

Abstract Elasticlave proposes a novel memory model for Trusted Execution Environments (TEEs) that overcomes the severe performance penalties associated with traditional spatial isolation models like Intel SGX. This innovation allows enclaves to selectively

By Admin 16 Oct 2020 • 2 min read •

Research

A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference (Full Report)

By Admin 8 Oct 2020 • 3 min read •

Research

A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference

Abstract This work introduces the MPIC (Mixed Precision Inference Core), a novel RISC-V processor designed to efficiently execute fine-grained mixed-precision Quantized Neural Networks (QNNs) on extreme-edge microcontrollers. It solves the challenge of supporting

By Admin 8 Oct 2020 • 2 min read •

Research

An Embedded RISC-V Core with Fast Modular Multiplication (Full Report)

By Admin 30 Sep 2020 • 3 min read •

Research

An Embedded RISC-V Core with Fast Modular Multiplication

Abstract This work introduces an embedded RISC-V core designed to address the security and power consumption challenges inherent in battery-operated IoT devices by accelerating cryptographic operations. The key innovation is an extended custom

By Admin 30 Sep 2020 • 2 min read •

Research

Enabling Virtual Memory Research on RISC-V with a Configurable TLB Hierarchy for the Rocket Chip Generator (Full Report)

By Admin 16 Sep 2020 • 3 min read •

Research

Enabling Virtual Memory Research on RISC-V with a Configurable TLB Hierarchy for the Rocket Chip Generator

Abstract This work enhances the RISC-V Rocket Chip Generator by implementing a configurable, set-associative Translation Lookaside Buffer (TLB) hierarchy within its Memory Management Unit. This innovation lifts the previous restrictions of fixed L1/

By Admin 16 Sep 2020 • 2 min read •

Research

A transprecision floating-point cluster for efficient near-sensor data analytics (Full Report)

By Admin 27 Aug 2020 • 3 min read •