Paper

Research

RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions

Abstract This paper proposes RVCoreP-32IC, a high-performance RISC-V soft processor targeting FPGAs, featuring a novel instruction fetch unit engineered to efficiently support compressed instructions (RVC). Although RVC reduces code size by about 25%

By Admin 23 Nov 2020 • 2 min read •

Research

SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation (Full Report)

By Admin 20 Nov 2020 • 3 min read •

Research

SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation

Abstract Microarchitectural timing attacks exploit shared on-core state components like caches and TLBs, which are traditionally mitigated inefficiently using software-based flushing instructions. This paper introduces SIMF (Single-Instruction Multiple-Flush), a specialized hardware mechanism implemented

By Admin 20 Nov 2020 • 2 min read •

Research

AXES: Approximation Manager for Emerging Memory Architectures (Full Report)

By Admin 17 Nov 2020 • 3 min read •

Research

AXES: Approximation Manager for Emerging Memory Architectures

Abstract AXES is the first self-optimizing runtime manager designed to coordinate configurable approximation knobs across all levels of the memory hierarchy, overcoming the limitations of rigid, design-time policies. It continuously learns and updates

By Admin 17 Nov 2020 • 2 min read •

Research

Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra (Full Report)

By Admin 16 Nov 2020 • 3 min read •

Research

Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra

Abstract This work introduces the Indirection Stream Semantic Register Architecture, an enhancement to a memory-streaming RISC-V ISA extension designed to efficiently handle sparse-dense linear algebra, which traditionally suffers from indirect memory lookup bottlenecks.

By Admin 16 Nov 2020 • 2 min read •

Research

RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors (Full Report)

By Admin 30 Oct 2020 • 3 min read •

Research

RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors

Abstract The RVCoreP-32IM architecture is proposed as an effective extension to the five-stage RVCoreP soft processor to efficiently implement the RISC-V M-extension (multiplication/division instructions). Utilizing a simple fork-join method to expand execution

By Admin 30 Oct 2020 • 1 min read •

Research

The nanoPU: Redesigning the CPU-Network Interface to Minimize RPC Tail Latency (Full Report)

By Admin 23 Oct 2020 • 3 min read •

Research

The nanoPU: Redesigning the CPU-Network Interface to Minimize RPC Tail Latency

Abstract The nanoPU is a new CPU architecture optimized for networking tasks, specifically designed to minimize tail latency for Remote Procedure Calls (RPCs). It achieves an extremely fast 65ns wire-to-wire latency—a 13x

By Admin 23 Oct 2020 • 2 min read •

Research

Composite Enclaves: Towards Disaggregated Trusted Execution (Full Report)

By Admin 20 Oct 2020 • 3 min read •