Paper

Research

A Novel Compaction Approach for SBST Test Programs

Abstract This work introduces a novel compaction strategy designed to significantly reduce the size and duration of Self-Test Library (STL) programs used for in-field testing of safety-critical processors. The approach

By Admin 2 Sep 2021 • 2 min read •

Research

Arrow: A RISC-V Vector Accelerator for Machine Learning Inference (Full Report)

By Admin 15 Jul 2021 • 3 min read •

Research

Arrow: A RISC-V Vector Accelerator for Machine Learning Inference

Abstract This paper introduces Arrow, a configurable hardware accelerator architecture implementing a subset of the RISC-V v0.9 vector ISA extension, specifically targeting edge machine learning inference. Benchmarked against fundamental vector and

By Admin 15 Jul 2021 • 1 min read •

Research

A Survey on RISC-V Security: Hardware and Architecture (Full Report)

By Admin 9 Jul 2021 • 3 min read •

Research

A Survey on RISC-V Security: Hardware and Architecture

Abstract This paper presents the first comprehensive survey of security solutions for the open RISC-V Instruction Set Architecture (ISA), addressing a critical research gap in the rapidly evolving IoT landscape. It analyzes

By Admin 9 Jul 2021 • 2 min read •

Research

Flare: Flexible In-Network Allreduce (Full Report)

By Admin 29 Jun 2021 • 3 min read •

Research

Flare: Flexible In-Network Allreduce

Abstract Flare is a flexible programmable switch designed to accelerate the computationally intensive allreduce communication operation in distributed systems by offloading aggregation to the network. Existing in-network solutions lack customization for specific

By Admin 29 Jun 2021 • 2 min read •

Research

Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection (Full Report)

By Admin 18 Jun 2021 • 3 min read •

Research

Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection

Abstract This paper introduces a novel pre-silicon verification approach that extends Symbolic Quick Error Detection (SQED) by incorporating symbolic starting states, effectively breaking the bounds of conventional verification. This methodology allows Bounded

By Admin 18 Jun 2021 • 2 min read •

Research

Towards Accurate Performance Modeling of RISC-V Designs (Full Report)

By Admin 18 Jun 2021 • 3 min read •

Research

Towards Accurate Performance Modeling of RISC-V Designs

Abstract This paper investigates the critical challenge of achieving high performance modeling accuracy using microarchitecture-level simulators, which traditionally prioritize speed over fidelity compared to RTL simulation. The authors conduct a detailed study

By Admin 18 Jun 2021 • 2 min read •

Research

Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities (Full Report)

By Admin 16 Jun 2021 • 3 min read •