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Paper

A Novel Compaction Approach for SBST Test Programs
Research

A Novel Compaction Approach for SBST Test Programs

Abstract This work introduces a novel compaction strategy designed to significantly reduce the size and duration of Self-Test Library (STL) programs used for in-field testing of safety-critical processors. The approach analyzes the interaction
By Admin • 2 min read •
A Survey on RISC-V Security: Hardware and Architecture
Research

A Survey on RISC-V Security: Hardware and Architecture

Abstract This paper presents the first comprehensive survey of security solutions for the open RISC-V Instruction Set Architecture (ISA), addressing a critical research gap in the rapidly evolving IoT landscape. It analyzes representative
By Admin • 2 min read •
Flare: Flexible In-Network Allreduce
Research

Flare: Flexible In-Network Allreduce

Abstract Flare is a flexible programmable switch designed to accelerate the computationally intensive allreduce communication operation in distributed systems by offloading aggregation to the network. Existing in-network solutions lack customization for specific data
By Admin • 2 min read •
Towards Accurate Performance Modeling of RISC-V Designs
Research

Towards Accurate Performance Modeling of RISC-V Designs

Abstract This paper investigates the critical challenge of achieving high performance modeling accuracy using microarchitecture-level simulators, which traditionally prioritize speed over fidelity compared to RTL simulation. The authors conduct a detailed study using
By Admin • 2 min read •
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