Paper
Research
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning
Abstract
This work addresses microarchitectural timing channels by proposing a systematic hardware defense mechanism based on full temporal partitioning. Leveraging the RISC-V ISA, the authors introduce a new temporal fence instruction, fence.
Research
CVA6's Data cache: Structure and Behavior
Abstract
This paper addresses the critical lack of detailed documentation regarding the data cache microarchitecture within the widely used RISC-V CVA6 core, a necessary precursor for successful security research. Since microarchitectural attacks
Research
CVA6's Data cache: Structure and Behavior
Originally published on ArXiv - Hardware Architecture
Computer Science > Cryptography and Security
arXiv:2202.03749v3 (cs)
[Submitted on 8 Feb 2022 (v1), last revised 5 Jul 2022 (this version, v3)]
Title:CVA6'
Research
DuVisor: a User-level Hypervisor Through Delegated Virtualization
Abstract
DuVisor introduces the concept of "delegated virtualization" to fundamentally redesign hypervisor architecture, achieving a purely user-level hypervisor by separating the control plane from the data plane. This design allows
Research
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode
Abstract
Dustin is a 16-core parallel ultra-low-power RISC-V cluster designed for edge devices, focusing on energy-intensive Deep Neural Network (DNN) workloads. Its key innovation is the support for
Research
HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing
Abstract
HEROv2 is an FPGA-based, full-stack, open-source research platform designed to enable fast and accurate exploration of heterogeneous computing architectures, circumventing the compromises of traditional simulators. It integrates application-class