Paper
Research
Architect in the Loop Agentic Hardware Design and Verification
Abstract
This paper proposes an "Architect in the Loop" agentic framework that automates the systematic and hierarchical design and verification of complex digital hardware, particularly processors. The methodology utilizes a combination
Research
ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
Abstract
ShuffleV is a novel microarchitectural defense strategy developed to counter Electromagnetic Side-Channel Attacks (EM SCAs) by adopting a Moving Target Defense (MTD) philosophy. It integrates hardware units into the open-source RISC-V core
Research
A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
Abstract
This paper introduces a novel Direct Memory Access Controller (DMAC) specifically optimized to efficiently handle arbitrary transfers of small unit sizes, addressing the inefficiency of classical descriptor-based DMACs in heterogeneous computing environments.
Research
Sequencing on Silicon: AI SoC Design for Mobile Genomics at the Edge
Abstract
This paper presents a specialized CMOS System-on-Chip (SoC) designed to handle the extremely high data rates of mobile nanopore DNA sequencing, advancing genomic analysis at the edge. The proposed architecture employs a
Research
A High-Efficiency SoC for Next-Generation Mobile DNA Sequencing
Abstract
This paper presents a high-efficiency System-on-Chip (SoC) designed to enable truly mobile, real-time DNA sequencing by overcoming the computational limits of current hand-sized machines that rely on external processing. The SoC is
Research
A Dense and Efficient Instruction Set Architecture Encoding
Abstract
This paper introduces Scry, a novel and experimental Instruction Set Architecture (ISA) designed to maximize instruction density and encoding efficiency for modern processor implementations. Scry achieves instruction-feature parity with RISC-V's