Paper
Research
ProSpeCT: Provably Secure Speculation for the Constant-Time Policy (Extended version)
Abstract
ProSpeCT is a generic formal processor model designed to provide provably secure speculative execution specifically for programs adhering to the constant-time policy. It guarantees security by tracking secret data within the pipeline
Research
ColibriES: A Milliwatts RISC-V Based Embedded System Leveraging Neuromorphic and Neural Networks Hardware Accelerators for Low-Latency Closed-loop Control Applications
Abstract
ColibriES is a novel milliwatt RISC-V based embedded system featuring the first-ever dedicated event-sensor interfaces and full neuromorphic processing pipelines. Built upon the Kraken System-on-Chip (SoC), it integrates a heterogeneous PULP processor
Research
RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption
Abstract
RISE is a novel RISC-V System-on-Chip (SoC) designed to accelerate critical message-to-ciphertext conversion operations for Homomorphic Encryption (HE) on resource-constrained edge devices. The architecture overcomes bottlenecks in error sampling and Number Theoretic
Research
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference
Abstract
Quark is an integer RISC-V vector processor specifically tailored for highly efficient sub-byte quantized Deep Neural Network (DNN) inference. Built upon the open-source Ara processor, Quark achieves significant area and power savings
Research
Adding Explicit Load-Acquire and Store-Release Instructions to the RISC-V ISA
Abstract
This paper proposes the addition of explicit load-acquire and store-release instructions to the RISC-V ISA, a crucial step for managing synchronization in architectures utilizing weak memory models. The authors demonstrate support by
Research
CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration
Abstract
This article describes the implementation and optimization of hardware virtualization support for the open-source RISC-V CVA6 core, encompassing architecture and microarchitecture enhancements. The authors introduce specific structures like the G-Stage TLB (GTLB)