Paper
Research
Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing
Abstract
This work, titled "Big-PERCIVAL," explores the native implementation and use of 64-bit posit arithmetic (posit64) and associated quire operations by extending the PERCIVAL RISC-V core and Xposit custom ISA. Results
Research
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra
Abstract
This paper introduces Sparse Stream Semantic Registers (SSSR), a lightweight ISA extension for RISC-V designed to accelerate general sparse linear algebra by efficiently handling both one- and two-sided operand sparsity. SSSR accelerates
Research
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In
Abstract
Cheshire is a lightweight, Linux-capable 64-bit RISC-V host platform designed to facilitate the seamless integration of domain-specific accelerators, targeting energy-constrained IoT and TinyML applications. Its core architectural features include a unique low-pin-count
Research
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS
Abstract
The Horizon Europe NEUROPULS project introduces novel secure and energy-efficient neuromorphic accelerators leveraging Phase Change Material (PCM) augmented silicon photonics technology. These accelerators are designed to interface seamlessly with RISC-V architectures via
Research
NPS: A Framework for Accurate Program Sampling Using Graph Neural Network
Abstract
Neural Program Sampling (NPS) is a novel framework that utilizes a Graph Neural Network (GNN) approach to accurately select representative simulation points, addressing the limitations and time-consuming manual tuning required by traditional
Research
CoVE: Towards Confidential Computing on RISC-V Platforms
Abstract
This paper introduces CoVE, a proposed reference architecture for implementing Confidential Computing on RISC-V platforms. It addresses the vulnerability of large Trusted Computing Bases (TCBs) in traditional multi-tenant environments by defining hardware-attested