Paper
Research
Octopus: A Heterogeneous In-network Computing Accelerator Enabling Deep Learning for network
Abstract
The Octopus accelerator addresses the challenge of deploying Deep Learning (DL) models directly onto programmable in-network computing devices, which typically lack the necessary processing power and generality. It employs a heterogeneous architecture
Research
Unlocking Hardware Security Assurance: The Potential of LLMs
Abstract
This paper introduces the Natural Language Processing-based Security Property Generator (NSPG), a novel automated method designed to enhance hardware security assurance in complex System-on-Chips (SoCs). NSPG utilizes HS-BERT, the first language model
Research
Towards a Formally Verified Security Monitor for VM-based Confidential Computing
Abstract
This paper proposes a novel methodology for formally modeling and proving a security monitor for VM-based confidential computing, addressing the lack of verification in existing systems critical for high-assurance applications. It introduces
Research
PPU: Design and Implementation of a Pipelined Full Posit Processing Unit
Abstract
This paper presents the design and integration of a Pipelined Full Posit Processing Unit (FPPU) into the low-power Ibex RISC-V core, leveraging the modular RISC-V ISA to enable customized posit arithmetic instructions.
Research
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
Abstract
SoftFlow is a novel Electronic Design Automation (EDA) tool designed to automate the confidentiality verification of sensitive data across the hardware-software boundary in embedded processors. It identifies whether specific software exploits existing
Research
SafeLS: Toward Building a Lockstep NOEL-V Core
Abstract
This paper presents SafeLS, an extension designed to integrate lockstep capabilities into Gaisler's NOEL-V RISC-V core for use in safety-critical systems. Lockstep architecture is employed to prevent Common Cause Failures