Paper

Research

STRELA: STReaming ELAstic CGRA Accelerator for Embedded Systems

Abstract STRELA is an elastic Coarse-Grained Reconfigurable Architecture (CGRA) integrated into an energy-efficient RISC-V System-on-Chip (SoC) designed for the embedded domain. Its microarchitecture specifically supports conditionals and irregular loops, enhancing adaptability for complex,

By Admin 18 Apr 2024 • 2 min read •

Research

Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach (Full Report)

By Admin 13 Apr 2024 • 3 min read •

Research

Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach

Abstract This paper addresses the deployment of intelligent Intrusion Detection Systems (I-IDS) on resource-constrained Edge hardware by proposing a systematic approach utilizing reconfigurable FPGA technology. The authors implemented and compared two architectures: a

By Admin 13 Apr 2024 • 2 min read •

Research

Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing (Full Report)

By Admin 10 Apr 2024 • 3 min read •

Research

Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing

Abstract This paper introduces ChatFuzz, a novel ML-based hardware fuzzer that leverages Large Language Models (LLMs) and Reinforcement Learning (RL) to efficiently generate effective assembly code sequences for processor verification. Utilizing the RISC-V

By Admin 10 Apr 2024 • 2 min read •

Research

Design and implementation of a synchronous Hardware Performance Monitor for a RISC-V space-oriented processor (Full Report)

By Admin 8 Apr 2024 • 3 min read •

Research

Design and implementation of a synchronous Hardware Performance Monitor for a RISC-V space-oriented processor

Abstract This paper details the design and implementation of a synchronous Hardware Performance Monitor (HPM), or Performance Measurement Unit (PMU), integrated into a RISC-V processor intended for space-oriented On-Board Computer (OBC) applications. The

By Admin 8 Apr 2024 • 2 min read •

Research

SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers (Full Report)

By Admin 8 Apr 2024 • 3 min read •

Research

SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers

Abstract SARIS is a general methodology leveraging register-mapped indirect streams to significantly accelerate performance-critical stencil computations on energy-efficient RISC-V compute clusters. Utilizing this technique on an eight-core system, the authors demonstrate an average

By Admin 8 Apr 2024 • 2 min read •

Research

QED: Scalable Verification of Hardware Memory Consistency (Full Report)

By Admin 3 Apr 2024 • 3 min read •

Research

QED: Scalable Verification of Hardware Memory Consistency

Abstract QED is a novel, scalable verification methodology designed to detect complex Memory Consistency Model (MCM) bugs in out-of-order (OOO) processors, surpassing the severe scaling limits of prior bounded verification techniques. It achieves

By Admin 3 Apr 2024 • 2 min read •

Research

Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices (Full Report)

By Admin 2 Apr 2024 • 3 min read •