Paper

Research

Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes

Abstract This paper presents a novel, software-friendly Near-Memory Computing (NMC) approach, featuring two scalable RISC-V programmable architectures, NM-Caesar and NM-Carus, designed to enhance energy efficiency in AI-driven edge nodes. These architectures offer low

By Admin 20 Jun 2024 • 2 min read •

Research

Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis (Full Report)

By Admin 14 Jun 2024 • 3 min read •

Research

Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis

Abstract This work tackles the limitations of proprietary GPGPU analysis tools by leveraging open-source hardware to enable deep micro-architecture parameter analysis. The authors introduce a hardware-aware, runtime mapping technique for OpenCL kernels validated

By Admin 14 Jun 2024 • 2 min read •

Research

Hypervisor Extension for a RISC-V Processor (Full Report)

By Admin 12 Jun 2024 • 2 min read •

Research

Hypervisor Extension for a RISC-V Processor

Abstract This paper documents the practical experience of implementing a Hypervisor extension specifically tailored for a 64-bit RISC-V processor architecture. The authors detail the comprehensive design process required to integrate virtualization support into

By Admin 12 Jun 2024 • 1 min read •

Research

A 0.96pJ/SOP, 30.23K-neuron/mm^2 Heterogeneous Neuromorphic Chip With Fullerene-like Interconnection Topology for Edge-AI Computing (Full Report)

By Admin 3 Jun 2024 • 3 min read •

Research

A 0.96pJ/SOP, 30.23K-neuron/mm^2 Heterogeneous Neuromorphic Chip With Fullerene-like Interconnection Topology for Edge-AI Computing

Abstract This work introduces a heterogeneous neuromorphic system-on-chip (SoC) designed for highly efficient Edge-AI computing, achieving an impressive energy consumption of 0.96 pJ/SOP. The architecture integrates a tightly coupled RISC-V CPU

By Admin 3 Jun 2024 • 2 min read •

Research

Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform (Full Report)

By Admin 29 May 2024 • 3 min read •

Research

Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform

Abstract This work presents the first end-to-end inference results of transformer Foundation Models on a general-purpose, open-source many-tiny-core RISC-V platform, leveraging specialized ISA extensions and distributed primitives. The optimized implementation achieves significant speedups

By Admin 29 May 2024 • 2 min read •

Research

xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems (Full Report)

By Admin 29 May 2024 • 3 min read •

Research

xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems

Abstract xTern is a lightweight RISC-V instruction set architecture extension designed to accelerate Ternary Neural Network (TNN) inference on general-purpose edge cores. This ISA extension, complemented by optimized kernels, achieves 67% higher throughput

By Admin 29 May 2024 • 2 min read •

Research

Full-stack evaluation of Machine Learning inference workloads for RISC-V systems (Full Report)

By Admin 24 May 2024 • 3 min read •