Paper
Research
RISC-V R-Extension: Advancing Efficiency with Rented-Pipeline for Edge DNN Processing
Abstract
This paper introduces the RISC-V R-extension, a novel architectural approach designed to enhance Deep Neural Network (DNN) processing efficiency on lightweight edge devices. The R-extension avoids the high power, cost, and area
Research
NoX: a Compact Open-Source RISC-V Processor for Multi-Processor Systems-on-Chip
Abstract
The NoX processor is a compact, open-source, 32-bit RISC-V core designed in System Verilog to serve as a plug-and-play solution for Multi-Processor Systems-on-Chip (MPSoCs) targeting edge computing and IoT applications. It utilizes
Research
Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor
Abstract
The paper details the design, implementation, and evaluation of the RISC-V SVNAPOT Extension, intended to reduce Memory Management Unit (MMU) overhead during heavy memory loads. This extension leverages larger 64KB Natural-Power-of-Two (NAPOT)
Research
Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS
Abstract
Basilisk is presented as the first end-to-end open-source, Linux-capable RISC-V System-on-Chip (SoC), successfully taped out utilizing IHP's open 130 nm CMOS technology. This achievement validates the capability of open-source hardware
Research
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET
Originally published on ArXiv - Hardware Architecture
Abstract
We present Occamy, a 432-core RISC-V dual-chiplet 2.5D system for efficient sparse linear algebra and stencil computations on FP64 and narrow (32-, 16-, 8-bit)
Research
RISC-V processor enhanced with a dynamic micro-decoder unit
Abstract
This paper assesses the benefits and costs of integrating a CISC-inspired dynamic micro-decoding unit into a standard RISC-V processor core. The unit is designed to sit within a specific pipeline stage, enabling