Paper

Research

FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support

Abstract FlooNoC is an open-source Network-on-Chip (NoC) designed specifically for the massive bulk data transfer demands of modern AI accelerators, featuring very wide, AXI4-compliant physical links. It achieves a leading energy efficiency of

By Admin 26 Sep 2024 • 2 min read •

Research

SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference (Full Report)

By Admin 21 Sep 2024 • 3 min read •

Research

SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference

Abstract SPEED is a scalable RISC-V Vector (RVV) processor designed to enable highly efficient multi-precision Deep Neural Network (MP-DNN) inference on resource-constrained edge platforms. It introduces dedicated customized RVV instructions and a parameterized

By Admin 21 Sep 2024 • 2 min read •

Research

Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction (Full Report)

By Admin 9 Aug 2024 • 3 min read •

Research

Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction

Abstract This study analyzes the MiG-V, the first commercially available logic-locked RISC-V processor, examining whether its logic locking mechanism impacts runtime data confidentiality. Researchers demonstrate a critical vulnerability by deliberately altering the logic

By Admin 9 Aug 2024 • 2 min read •

Research

Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction

Originally published on ArXiv - Hardware Architecture Computer Science > Cryptography and Security arXiv:2408.04976v1 (cs) [Submitted on 9 Aug 2024] Title:Exploiting the Lock: Leveraging MiG-V's Logic Locking for

By Admin 9 Aug 2024 • 5 min read •

Research

Deeploy: Enabling Energy-Efficient Deployment of Small Language Models On Heterogeneous Microcontrollers (Full Report)

By Admin 8 Aug 2024 • 3 min read •

Research

Deeploy: Enabling Energy-Efficient Deployment of Small Language Models On Heterogeneous Microcontrollers

Abstract Deeploy is a novel Deep Neural Network (DNN) compiler enabling the energy-efficient, end-to-end deployment of Small Language Models (SLMs) directly onto heterogeneous microcontroller (MCU) class chips without relying on external high-bandwidth memory.

By Admin 8 Aug 2024 • 2 min read •

Research

Toward Attention-based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow (Full Report)

By Admin 5 Aug 2024 • 3 min read •

Research

Toward Attention-based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow

Abstract This work addresses the difficulty of running modern Attention-based Transformer models in resource-constrained Tiny Machine Learning (tinyML) environments. The authors introduce a heterogeneous RISC-V architecture, featuring an octa-core cluster coupled with a

By Admin 5 Aug 2024 • 2 min read •

Research

Functional ISS-Driven Verification of Superscalar RISC-V Processors (Full Report)

By Admin 30 Jul 2024 • 3 min read •

Research

Functional ISS-Driven Verification of Superscalar RISC-V Processors

Abstract This paper introduces SupeRFIVe, a novel methodology designed for the time-efficient and comprehensive functional verification of complex superscalar processors. SupeRFIVe leverages an Instruction Set Simulator (ISS) as a golden reference, interfacing with

By Admin 30 Jul 2024 • 1 min read •