Paper
Research
ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package
Abstract
ControlPULPlet is an open-source, real-time multi-core RISC-V controller designed specifically to manage coupled operation within 2.5D Systems-in-Package (SiP). The architecture minimizes performance penalties from die-to-die communication by integrating a 32-bit CV32RT
Research
Per-Bank Bandwidth Regulation of Shared Last-Level Cache for Real-Time Systems
Abstract
This paper addresses critical timing predictability issues in multicore real-time systems caused by cache bank contention and malicious bank-aware Denial-of-Service (DoS) attacks in shared Last-Level Caches (LLCs). The authors propose a novel
Research
Work-in-Progress: Real-Time Neural Network Inference on a Custom RISC-V Multicore Vector Processor
Abstract
This work presents a custom RISC-V multicore vector processor architecture combined with a novel compiler-based deployment toolchain tailored for real-time neural network inference. The design addresses the gap between high-performance accelerators (which
Research
RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective
Abstract
This paper critically analyzes the limitations of current RISC-V Instruction Set Architectures (ISA), including the upcoming WorldGuard technology, in meeting the strict cyber-security requirements of modern, virtualized automotive microcontroller units (MCUs) mandated
Research
RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective
Originally published on ArXiv - Hardware Architecture
Computer Science > Cryptography and Security
arXiv:2410.09839v1 (cs)
[Submitted on 13 Oct 2024]
Title:RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective
Research
RISC-V V Vector Extension (RVV) with reduced number of vector registers
Abstract
This work proposes reducing the area overhead of the RISC-V V Vector Extension (RVV) specifically for use in small processors. The innovation is centered on reducing the standard 32 vector registers to