Paper
Research
RISC-V Word-Size Modular Instructions for Residue Number Systems
Abstract
This article introduces and evaluates specific word-size modular arithmetic instructions designed for the RISC-V Instruction Set Architecture (ISA) to significantly enhance the software implementation of Residue Number Systems (RNS), which are critical
Research
Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension
Abstract
This paper presents the successful implementation and rigorous evaluation of the RISC-V H (hypervisor) extension within the gem5 microarchitectural simulator. This integration is crucial for enhancing RISC-V's capabilities in cloud
Research
OpenGeMM: A High-Utilization GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling
Abstract
OpenGeMM is an open-source acceleration platform designed to address the high-utilization challenges of generic RISC-V systems when running DNNs on resource-constrained edge devices. It integrates a parameterized Chisel-coded GeMM core, a lightweight
Research
Web-Based Simulator of Superscalar RISC-V Processors
Abstract
This paper presents an advanced, web-based simulator designed to help students and professionals master the fundamentals of superscalar RISC-V processors, HW/SW co-design, and HPC optimization. The tool features customizable processor and
Research
Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection
Abstract
Specure is a novel pre-silicon verification framework that addresses speculative execution vulnerabilities by combining hardware fuzzing with Information Flow Tracking (IFT). This hybrid approach enables automatic leakage detection without needing a golden
Research
Exploiting long vectors with a CFD code: a co-design show case
Abstract
This paper showcases a co-design methodology utilizing iterative analysis and compiler autovectorization to effectively exploit long vector architectures in HPC applications, specifically a production CFD code. The optimization process, designed to maximize