Paper

Research

Efficient Architecture for RISC-V Vector Memory Access

Abstract Vector processors frequently suffer from inefficient memory accesses, particularly for strided and segment patterns, often relying on high-overhead crossbars or large transposition buffers. This paper presents EARTH, a novel RISC-V vector memory

By Admin 11 Apr 2025 • 2 min read •

Research

Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication (Full Report)

By Admin 10 Apr 2025 • 3 min read •

Research

Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication

Abstract This study introduces the Cartesian Accumulative Matrix Pipeline (CAMP) architecture, a novel design leveraging a hybrid multiplier to significantly enhance matrix multiplication within Vector Architectures (VAs) and SIMD units, optimized for Quantized

By Admin 10 Apr 2025 • 2 min read •

Research

Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications (Full Report)

By Admin 10 Apr 2025 • 3 min read •

Research

Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications

Abstract Quadrilatero is an open-source RISC-V programmable matrix coprocessor designed to optimize AI workloads in low-power edge applications. It utilizes a systolic array architecture and a streamlined matrix ISA extension to overcome the

By Admin 10 Apr 2025 • 2 min read •

Research

Just TestIt! An SBST Approach To Automate System-Integration Testing (Full Report)

By Admin 10 Apr 2025 • 3 min read •

Research

Just TestIt! An SBST Approach To Automate System-Integration Testing

Abstract This paper introduces TestIt, an open-source Python package designed to automate full-system integration testing using a Software-Based Self-Test (SBST) approach. TestIt dynamically generates test vectors and golden references, significantly reducing development complexity

By Admin 10 Apr 2025 • 2 min read •

Research

ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes (Full Report)

By Admin 9 Apr 2025 • 3 min read •

Research

ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes

Abstract ShadowBinding proposes effective microarchitectures for state-of-the-art secure speculation schemes, such as Speculative Taint Tracking (STT) and Non-Speculative Data Access (NDA), addressing crucial performance bottlenecks in wide cores. The study reveals that rename-based

By Admin 9 Apr 2025 • 2 min read •

Research

SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions (Full Report)

By Admin 8 Apr 2025 • 3 min read •

Research

SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions

Abstract This paper presents SpikeStream, an optimization technique designed to accelerate Spiking Neural Network (SNN) inference on general-purpose RISC-V multicore clusters using a low-overhead ISA extension for sparse computation streaming. SpikeStream maps weight

By Admin 8 Apr 2025 • 2 min read •

Research

CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor (Full Report)

By Admin 8 Apr 2025 • 3 min read •