Paper
Research
Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS
Abstract
The Basilisk project introduces the largest end-to-end open-source system-on-chip (SoC) to date, successfully integrating a 64-bit Linux-capable RISC-V core on a 34 mm² die. Implemented in 130 nm BiCMOS technology, this effort
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Area Comparison of CHERIoT and PMP in Ibex
Abstract
This paper analyzes the hardware area cost of implementing Physical Memory Protection (PMP) and the CHERIoT capability-based security extension within the Ibex RISC-V core. Synthesis results show that PMP (16 regions) adds
Research
e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
Abstract
This work introduces e-GPU, an open-source and highly configurable RISC-V Graphic Processing Unit designed to deliver parallel acceleration to ultra-low-power TinyAI devices. The platform utilizes a lightweight Tiny-OpenCL framework for programming and
Research
Efficient Implementation of RISC-V Vector Permutation Instructions
Abstract
The efficient hardware implementation of RISC-V Vector (RVV) permutation instructions is complicated by their diverse control mechanisms, despite their necessity for accelerating data-parallel workloads like cryptography. This paper proposes a unified microarchitecture
Research
Assessing Tenstorrent's RISC-V MatMul Acceleration Capabilities
Abstract
This paper evaluates the performance and energy efficiency of the Tenstorrent Grayskull e75 RISC-V accelerator when executing fundamental MatMul operations critical for Large Language Models. Researchers conducted a detailed characterization of the
Research
Assessing Tenstorrent's RISC-V MatMul Acceleration Capabilities
Originally published on ArXiv - Hardware Architecture
Computer Science > Performance
arXiv:2505.06085v3 (cs)
[Submitted on 9 May 2025 (v1), last revised 20 Jun 2025 (this version, v3)]
Title:Assessing Tenstorrent'