Paper
Research
Introducing Instruction-Accurate Simulators for Performance Estimation of Autotuning Workloads
Abstract
This paper introduces a novel interface enabling autotuning workloads, critical for optimizing Machine Learning, to execute efficiently on instruction-accurate simulators rather than scarce target hardware. By training machine learning predictors on simulation
Research
MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products
Abstract
MXDOTP is a novel RISC-V ISA extension designed to accelerate dot product computations using the energy-efficient and highly accurate 8-bit Microscaling Floating-Point (MXFP8) format. The extension integrates a specialized MXFP8 dot product-accumulate
Research
AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security
Abstract
The AES-RV paper presents a hardware-efficient RISC-V accelerator featuring custom, low-latency AES instruction extensions optimized for real-time cryptographic processing in IoT systems. The architecture integrates high-bandwidth buffers, a specialized AES unit, and
Research
Scalable 28nm IC implementation of coupled oscillator network featuring tunable topology and complexity
Abstract
This work introduces a scalable, 28nm integrated circuit implementation of a coupled oscillator network designed to efficiently simulate complex dynamical systems for applications like analog computing and transport network stability analysis. The
Research
Enabling Syscall Intercept for RISC-V
Abstract
This paper details the efforts involved in porting a widely used syscall interception library to the RISC-V Instruction Set Architecture. The work is crucial for maturing the RISC-V software stack, enabling complex
Research
An Integrated UVM-TLM Co-Simulation Framework for RISC-V Functional Verification and Performance Evaluation
Abstract
This paper introduces an integrated UVM-TLM co-simulation framework designed to efficiently verify complex RISC-V processors by simultaneously evaluating functional correctness and performance. The methodology employs a configurable Transaction-Level Model (vmodel) of a