Paper

Research

HetGPU: The pursuit of making binary compatibility towards GPUs

Abstract HetGPU is a novel system designed to overcome the challenge of binary incompatibility across heterogeneous GPU vendors, including NVIDIA, AMD, Intel, and Tenstorrent. The system employs a compiler to generate an architecture-agnostic

By Admin 19 Jun 2025 • 2 min read •

Research

Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration (Full Report)

By Admin 18 Jun 2025 • 3 min read •

Research

Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration

Abstract Acore-CIM introduces a self-calibrated mixed-signal Compute-In-Memory (CIM) System-on-Chip (SoC) designed to overcome the integration and reliability challenges of analog AI accelerators. The architecture pairs dense SRAM weight storage with linear resistors for

By Admin 18 Jun 2025 • 2 min read •

Research

FeNN: A RISC-V vector processor for Spiking Neural Network acceleration (Full Report)

By Admin 13 Jun 2025 • 3 min read •

Research

FeNN: A RISC-V vector processor for Spiking Neural Network acceleration

Abstract The FeNN processor is a novel RISC-V-based soft vector processor specifically tailored for simulating energy-efficient Spiking Neural Networks (SNNs) on FPGAs. Unlike mainstream accelerators, FeNN is optimized for the low arithmetic intensity

By Admin 13 Jun 2025 • 2 min read •

Research

FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators (Full Report)

By Admin 13 Jun 2025 • 3 min read •

Research

FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators

Abstract FractalSync is a novel hardware-accelerated synchronization mechanism designed to address the challenges of coordinating massive parallel processing elements in Bulk Synchronous Parallel (BSP) AI accelerators. Integrated into the RISC-V based MAGIA platform,

By Admin 13 Jun 2025 • 2 min read •

Research

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration (Full Report)

By Admin 12 Jun 2025 • 3 min read •

Research

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration

Abstract This paper presents microarchitectural optimizations for energy-efficient RISC-V clusters aimed at achieving near zero-stall matrix multiplication for machine learning workloads. Key innovations include "zero-overhead loop nests" and a novel "

By Admin 12 Jun 2025 • 2 min read •

Research

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm (Full Report)

By Admin 9 Jun 2025 • 3 min read •

Research

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm

Abstract FREESS is a new free, interactive educational simulator designed to teach instruction-level parallelism in advanced computer architecture courses. It models a RISC-V-inspired superscalar processor utilizing an extended Tomasulo's algorithm for

By Admin 9 Jun 2025 • 1 min read •

Research

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm

Originally published on ArXiv - Hardware Architecture Computer Science > Hardware Architecture arXiv:2506.07665v1 (cs) [Submitted on 9 Jun 2025] Title:FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on

By Admin 9 Jun 2025 • 4 min read •