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RISC-V Acceleration for Deep Learning at the Edge - Electropages
Abstract
The article discusses the growing utilization of the open RISC-V Instruction Set Architecture (ISA) coupled with specialized hardware accelerators to meet the demanding requirements of Deep Learning inference at the edge. By
Research
Chip Industry Technical Paper Roundup: Sept 23 - Semiconductor Engineering
Abstract
The analysis of the 'Chip Industry Technical Paper Roundup: Sept 23' is incomplete because the actual text content of the summarized technical papers was not provided, only the title and
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HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.) - Semiconductor Engineering
Abstract
The research by Tampere University introduces an HW/SW co-design methodology aimed at efficiently integrating custom instruction set extensions (ISEs) into RISC-V cores. This approach specifically focuses on solving the typically time-consuming
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RISC-V: Shaping the Future of Mobility with Open Standards - EE Times
Abstract
RISC-V is emerging as the essential open standard architecture driving the future of mobility, specifically targeting advanced automotive applications like ADAS and high-performance computing in vehicles. The modular and customizable nature of
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Condor Technology To Fly “Cuzco” RISC-V CPU Into The Datacenter - The Next Platform
Abstract
Condor Technology is making a significant push into the competitive datacenter market with the introduction of its high-performance RISC-V CPU, codenamed "Cuzco." This development signals the maturity of the RISC-V
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SiFive Launches New RISC-V AI IP with Scalar, Vector, and Matrix Compute - eeNews Europe
Abstract
SiFive has launched a new specialized RISC-V Intellectual Property (IP) core explicitly designed to accelerate Artificial Intelligence (AI) workloads. This new IP solution integrates comprehensive processing capabilities, combining traditional scalar processing with