Architecture
Research
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications
Abstract
X-HEEP is an open-source, configurable RISC-V platform specifically designed for ultra-low-power edge applications (TinyAI). Its key innovation is the eXtendible Accelerator InterFace (XAIF), which enables seamless, highly customizable integration of diverse accelerators,
Research
Targeted Wearout Attacks in Microprocessor Cores
Originally published on ArXiv - Hardware Architecture
Computer Science > Cryptography and Security
arXiv:2508.16868v1 (cs)
[Submitted on 23 Aug 2025]
Title:Targeted Wearout Attacks in Microprocessor Cores
Authors:Joshua Mashburn, Johann
Research
Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference
Abstract
This paper introduces a novel System-on-Chip (SoC) architecture that tightly couples a 32-bit Codasip uRISC_V core with the open-source NVDLA for efficient deep learning inference on edge devices. The core innovation
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Research
Neural Network Quantization for Microcontrollers: A Comprehensive Survey of Methods, Platforms, and Applications
Abstract
This comprehensive survey addresses the challenges of deploying Quantized Neural Networks (QNNs) on resource-constrained microcontrollers (MCUs) within the TinyML paradigm. It systematically reviews hardware-oriented quantization methods, focusing on the critical trade-offs between
Research
IzhiRISC-V -- a RISC-V-based Processor with Custom ISA Extension for Spiking Neuron Networks Processing with Izhikevich Neurons
Abstract
This paper presents IzhiRISC-V, a specialized RISC-V-compliant processor engineered to overcome the inherent inefficiency of running Spiking Neural Networks (SNNs) on general-purpose hardware. The core innovation is a custom Instruction Set Architecture
Research
ARISE: Automating RISC-V Instruction Set Extension
Abstract
RISC-V's flexibility for custom instruction set extension (ISE) is often hindered by significant manual effort. The tool ARISE automates the generation of optimized RISC-V instructions by analyzing common assembly patterns