Architecture
Research
Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors
Abstract
Designing Application-Specific Instruction Set Processors (ASIPs) requires the manual identification of performance-enhancing custom instructions, a process addressed by this work's new automation tool. The paper introduces CIDRE (Custom Instruction Designer
Research
MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration
Abstract
MaRVIn is a cross-layer hardware-software co-design framework that introduces novel ISA extensions and micro-architectural enhancements to optimize mixed-precision Deep Neural Network (DNN) inference on RISC-V processors. It tackles the inefficiency of standard
Research
SuperUROP: An FPGA-Based Spatial Accelerator for Sparse Matrix Operations
Abstract
Solving sparse linear systems is critical in numerical methods but suffers from poor data reuse and complex dependencies on current hardware. This paper presents SuperUROP, an FPGA implementation of the Azul spatial
Research
TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
Abstract
TurboFuzz is an end-to-end hardware-accelerated verification framework that leverages a single FPGA to integrate the entire Test Generation, Simulation, and Coverage Feedback loop for modern processors. This architecture eliminates high host-FPGA communication
Research
Decentor-V: Lightweight ML Training on Low-Power RISC-V Edge Devices
Abstract
This paper introduces Decentor-V, a framework that enables lightweight Machine Learning training directly on low-power RISC-V edge devices, overcoming the architectural limitation imposed by the absence of dedicated Floating-Point Units (FPUs). By
Research
FASE: FPGA-Assisted Syscall Emulation for Rapid End-to-End Processor Performance Validation
Abstract
FASE (FPGA-Assisted Syscall Emulation) is a novel framework enabling rapid, early-stage processor performance validation by running complex multi-thread benchmarks directly on FPGA-hosted designs, bypassing the need for full SoC integration or a