Architecture

Research

Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator

Abstract This paper details the formal verification of WARP-V, an open-source RISC-V core generator developed using the timing-abstract, transaction-level TL-Verilog methodology. The verification employed the established riscv-formal framework, investigating the synergy between transaction-level

By Admin 5 Nov 2018 • 1 min read •

Research

CIDPro: Custom Instructions for Dynamic Program Diversification (Full Report)

By Admin 4 Sep 2018 • 3 min read •

Research

CIDPro: Custom Instructions for Dynamic Program Diversification

Abstract CIDPro is a novel framework that uses dynamic program diversification and custom instruction generation to mitigate timing side-channel attacks in embedded systems. It integrates the LLVM compiler and the RISC-V FPGA soft-processor,

By Admin 4 Sep 2018 • 2 min read •

Research

The BaseJump Manycore Accelerator Network (Full Report)

By Admin 2 Aug 2018 • 3 min read •

Research

The BaseJump Manycore Accelerator Network

Abstract The BaseJump Manycore Accelerator Network is an open-source, mesh-based On-Chip-Network (OCN) developed using over 20 years of manycore architecture expertise. This scalable network served as the communication backbone for the 16nm 511-core

By Admin 2 Aug 2018 • 2 min read •

Research

A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets (Full Report)

By Admin 19 Feb 2018 • 3 min read •

Research

A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets

Abstract This paper proposes NTX, a scalable near-memory acceleration engine designed for high-precision training of deep neural networks, moving beyond the traditional focus on inference acceleration. NTX is implemented on the Logic Base

By Admin 19 Feb 2018 • 2 min read •

Research

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification (Full Report)

By Admin 3 Jan 2018 • 3 min read •

Research

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification

Abstract Modern Systems-on-Chip (SoC) designs require a new verification standard due to their heterogeneity and reliance on specialized accelerators, which traditional Instruction Set Architectures (ISA) fail to cover. This paper formalizes the Instruction-Level

By Admin 3 Jan 2018 • 2 min read •

Research

HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA (Full Report)

By Admin 18 Dec 2017 • 3 min read •

Research

HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA

Abstract HERO is an FPGA-based heterogeneous embedded research platform designed to combine an industry-standard host processor with an open, scalable programmable manycore accelerator (PMCA). The platform integrates a hard ARM Cortex-A multicore host

By Admin 18 Dec 2017 • 2 min read •

Research

The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes (Full Report)

By Admin 13 Dec 2017 • 3 min read •