Architecture
Research
A Dense and Efficient Instruction Set Architecture Encoding
Abstract
This paper introduces Scry, a novel and experimental Instruction Set Architecture (ISA) designed to maximize instruction density and encoding efficiency for modern processor implementations. Scry achieves instruction-feature parity with RISC-V&
Research
A Compact, Low Power Transprecision ALU for Smart Edge Devices
Abstract
This work introduces TALU, a novel ASIC design for a Transprecision Arithmetic and Logic Unit tailored for energy-efficient machine learning on smart edge devices. TALU supports Posit, Floating Point, and Integer
Research
Runtime Energy Monitoring for RISC-V Soft-Cores
Abstract
This paper introduces a holistic hardware-based approach for runtime energy monitoring specifically targeting RISC-V soft-cores implemented on FPGAs. The proposed system utilizes a dedicated measurement board coupled with an
Research
ZynqParrot: A Scale-Down Approach to Cycle-Accurate, FPGA-Accelerated Co-Emulation
Abstract
ZynqParrot is an FPGA-accelerated co-emulation platform utilizing a novel "Scale-Down" approach for processor validation. This methodology decomposes large designs into manageable, independently prototyped sub-components, overcoming the
Research
Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
Abstract
This paper addresses the need for robust, pedagogically sound, and accessible RISC-V processor implementations for computer science education. The authors propose criteria for evaluating educational RISC-V ecosystems and analyze existing
Research
Chiplet-Based RISC-V SoC with Modular AI Acceleration
Abstract
This paper introduces a novel chiplet-based RISC-V System-on-Chip designed to overcome the low manufacturing yields and rigidity of monolithic edge AI devices by utilizing a 30mm x 30mm