Architecture

Research

CodeAPeel: An Integrated and Layered Learning Technology For Computer Architecture Courses

Abstract CodeAPeel is a novel, multi-layered learning technology for computer architecture courses that simulates instruction processing across compiler, assembly, and machine layers. Unlike simulators modeling real processors (e.g., RISC-V), CodeAPeel utilizes a

By Admin 18 Apr 2021 • 1 min read •

Research

A First Look at RISC-V Virtualization from an Embedded Systems Perspective (Full Report)

By Admin 27 Mar 2021 • 3 min read •

Research

A First Look at RISC-V Virtualization from an Embedded Systems Perspective

Abstract This article describes the first public implementation and evaluation of the RISC-V Hypervisor Extension (H-extension v0.6.1) targeting embedded and mixed-criticality systems on a Rocket chip core. The work successfully ported

By Admin 27 Mar 2021 • 2 min read •

Research

Comparative Analysis and Enhancement of CFG-based Hardware-Assisted CFI Schemes (Full Report)

By Admin 7 Mar 2021 • 3 min read •

Research

Comparative Analysis and Enhancement of CFG-based Hardware-Assisted CFI Schemes

Abstract This paper addresses the difficulty of quantitatively comparing existing hardware-assisted Control Flow Integrity (CFI) schemes by implementing several promising CFG-based mechanisms on a unified RISC-V platform. The authors benchmark performance, hardware utilization,

By Admin 7 Mar 2021 • 2 min read •

Research

Brightening the Optical Flow through Posit Arithmetic (Full Report)

By Admin 17 Jan 2021 • 3 min read •

Research

Brightening the Optical Flow through Posit Arithmetic

Abstract This paper investigates the commercial and technical merits of the posit data format as a drop-in replacement for the IEEE 754 floating-point standard, specifically applying it to the Lucas-Kanade (LuKa) optical flow

By Admin 17 Jan 2021 • 2 min read •

Research

ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework (Full Report)

By Admin 14 Jan 2021 • 3 min read •

Research

ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework

Abstract ANDROMEDA is an FPGA-based framework designed for the exploration and optimization of complex RISC-V Multiprocessor Systems-on-Chip (MPSoCs). It enables computer architects to vary and observe the performance trade-offs of critical parameters, including

By Admin 14 Jan 2021 • 1 min read •

Research

Efficient Sealable Protection Keys for RISC-V (Full Report)

By Admin 4 Dec 2020 • 3 min read •

Research

Efficient Sealable Protection Keys for RISC-V

Abstract This paper proposes SealPK, an efficient hardware-assisted intra-process isolation mechanism for the RISC-V open ISA, designed to overcome limitations found in modern processors like Intel MPK. SealPK dramatically expands domain capacity to

By Admin 4 Dec 2020 • 2 min read •

Research

XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes (Full Report)

By Admin 29 Nov 2020 • 3 min read •