Architecture

Research

Towards Accurate Performance Modeling of RISC-V Designs

Abstract This paper investigates the critical challenge of achieving high performance modeling accuracy using microarchitecture-level simulators, which traditionally prioritize speed over fidelity compared to RTL simulation. The authors conduct a detailed study using

By Admin 18 Jun 2021 • 2 min read •

Research

Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities (Full Report)

By Admin 16 Jun 2021 • 3 min read •

Research

Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities

Abstract This paper presents a comprehensive study of security vulnerabilities in modern RISC-V microprocessors stemming from side-channel attacks (SCAs) and their corresponding mitigation techniques. The analysis focuses on both hardware-exploitable attacks, specifically using

By Admin 16 Jun 2021 • 2 min read •

Research

Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions (Full Report)

By Admin 14 Jun 2021 • 3 min read •

Research

Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions

Abstract This paper presents a novel set of non-standard vector instruction types designed to extend the RISC-V ISA for exploring advanced, reconfigurable SIMD operations. The authors introduce a high-performance, open-source RV32 IM softcore

By Admin 14 Jun 2021 • 2 min read •

Research

Isadora: Automated Information Flow Property Generation for Hardware Designs (Full Report)

By Admin 14 Jun 2021 • 3 min read •

Research

Isadora: Automated Information Flow Property Generation for Hardware Designs

Abstract Isadora is an automated methodology designed to generate information flow specifications for hardware designs, eliminating the need for manual security specifications or threat models. It operates by combining information flow tracking and

By Admin 14 Jun 2021 • 2 min read •

Research

HeapSafe: Securing Unprotected Heaps in RISC-V (Full Report)

By Admin 18 May 2021 • 3 min read •

Research

HeapSafe: Securing Unprotected Heaps in RISC-V

Abstract HeapSafe is a novel, lightweight hardware-assisted security scheme designed to mitigate critical memory corruption vulnerabilities, such as heap overflow and use-after-free, in bare-metal RISC-V systems. The approach utilizes a configurable coprocessor, decoupled

By Admin 18 May 2021 • 2 min read •

Research

MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations (Full Report)

By Admin 17 May 2021 • 4 min read •

Research

MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations

Abstract MetaSys is the first open-source, FPGA-based infrastructure, prototyped within a RISC-V core, designed to enable the rapid implementation and evaluation of diverse cross-layer hardware-software optimizations. It introduces a lightweight, generalized metadata management

By Admin 17 May 2021 • 2 min read •

Research

CodeAPeel: An Integrated and Layered Learning Technology For Computer Architecture Courses (Full Report)

By Admin 18 Apr 2021 • 3 min read •