Architecture

Research

Experimental evaluation of neutron-induced errors on a multicore RISC-V platform (Full Report)

By Admin 17 Jun 2022 • 3 min read •

Research

Experimental evaluation of neutron-induced errors on a multicore RISC-V platform

Abstract This study experimentally evaluates neutron-induced soft errors on the GAP8 multicore RISC-V ASIC platform, addressing the need for reliability data in safety-critical domains. The research found that computing-intensive applications, specifically Convolutional Neural

By Admin 17 Jun 2022 • 2 min read •

Research

CuPBoP: CUDA for Parallelized and Broad-range Processors (Full Report)

By Admin 16 Jun 2022 • 3 min read •

Research

CuPBoP: CUDA for Parallelized and Broad-range Processors

Abstract CuPBoP (CUDA for Parallelized and Broad-range Processors) is a novel framework designed to execute proprietary CUDA code on non-NVIDIA hardware, addressing the limitations of vendor lock-in and enabling data-parallel computing in heterogeneous

By Admin 16 Jun 2022 • 2 min read •

Research

Muntjac -- Open Source Multicore RV64 Linux-capable SoC (Full Report)

By Admin 14 Jun 2022 • 2 min read •

Research

Muntjac -- Open Source Multicore RV64 Linux-capable SoC

Abstract Muntjac is an open-source collection of components utilized to construct a multicore, Linux-capable System-on-Chip (SoC). This design incorporates a 64-bit RISC-V core and a cache subsystem, leveraging the TileLink interconnect to achieve

By Admin 14 Jun 2022 • 1 min read •

Research

Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP (Full Report)

By Admin 4 Jun 2022 • 3 min read •

Research

Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP

Abstract This paper addresses the scarcity of open-source SoC platforms capable of integrating the growing number of open-source RISC-V processors for heterogeneous designs. The authors present modifications to ESP, an open-source SoC platform,

By Admin 4 Jun 2022 • 1 min read •

Research

Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference (Full Report)

By Admin 3 Jun 2022 • 3 min read •

Research

Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference

Abstract Analog In-Memory Computing (AIMC) scalability is limited by the massive bandwidth and low latency required for on-chip communication, which traditional infrastructure cannot support. This work introduces a many-tile AIMC architecture that resolves

By Admin 3 Jun 2022 • 2 min read •

Research

PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques (Full Report)

By Admin 1 Jun 2022 • 3 min read •

Research

PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques

Abstract PiDRAM is the first flexible, end-to-end, and open-source FPGA-based framework enabling the evaluation of real Processing-in-DRAM (PiM) techniques using real DRAM chips. The framework is prototyped on a Xilinx ZC706 FPGA, integrated

By Admin 1 Jun 2022 • 2 min read •