Architecture
Research
Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs
Abstract
Kraken is an ultra-low-power, heterogeneous System-on-Chip (SoC) fabricated in 22nm FDX technology designed to enable complex, autonomous visual tasks for Nano-UAVs under tight power constraints. The chip achieves high-speed, multi-functional visual processing
Research
An Enclave-based TEE for SE-in-SoC in RISC-V Industry
Abstract
This work introduces an Enclave-based Trusted Execution Environment (TEE) designed to secure integrated Secure Elements (SE) within RISC-V Systems-on-Chip (SoC). Addressing the rising complexity and security flaws of traditional SE-in-SoC designs, the
Research
Static Hardware Partitioning on RISC-V -- Shortcomings, Limitations, and Prospects
Abstract
This paper investigates the viability of static hardware partitioning (SHP) on multi-core RISC-V processors essential for consolidating mixed-criticality and real-time embedded workloads while ensuring freedom from interference. The authors identify significant shortcomings
Research
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters
Abstract
Spatz is a novel, compact 32-bit vector processing unit designed as an energy-efficient Processing Element for large-scale clusters leveraging shared L1 memory, specifically targeting mitigation of the Von Neumann Bottleneck. Built upon
Research
ERIC: An Efficient and Practical Software Obfuscation Framework
Abstract
ERIC is an efficient and general software obfuscation framework designed to protect distributed software executables against both static and dynamic analysis. It leverages Physical Unclonable Functions (PUFs) to generate unique device identifiers
Research
MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores
Abstract
This paper introduces MiniFloat-NN, a RISC-V Instruction Set Architecture (ISA) extension, and ExSdotp, a modular open hardware unit, designed to accelerate low-precision neural network training using 8-bit and 16-bit floating-point formats. The