Architecture
Research
Pushing the Limits of Machine Design: Automated CPU Design with AI
Abstract
This paper presents a novel AI approach that autonomously designs an industrial-scale Central Processing Unit (CPU) solely from external input-output observations, navigating an unprecedented search space of $10^{10^{540}}$. Using a
Research
Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference
Abstract
Sparq is a custom RISC-V vector processor designed specifically to accelerate highly efficient sub-byte Quantized Neural Network (QNN) inference. This architecture modifies the open-source Ara core by removing the Floating-Point Unit and
Research
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
Abstract
ControlPULP is an open-source, HW/SW RISC-V parallel Power Controller System (PCS) designed to manage complex, real-time closed-loop power and thermal requirements in many-core HPC processors. The architecture utilizes a single-core MCU
Research
ColibriUAV: An Ultra-Fast, Energy-Efficient Neuromorphic Edge Processing UAV-Platform with Event-Based and Frame-Based Cameras
Abstract
ColibriUAV is an ultra-fast, energy-efficient UAV platform that combines traditional frame-based cameras with dynamic vision sensors (DVS) for robust, low-latency perception. The system is centered around Kraken, a novel low-power RISC-V System
Research
A Classical Architecture For Digital Quantum Computers
Abstract
This paper presents a scalable classical control architecture for digital quantum computers, tackling major scaling bottlenecks by integrating a multi-core RISC-V CPU with in-house control electronics. The architecture features parallel quantum operation
Research
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing
Abstract
Marsellus is a heterogeneous RISC-V System-on-a-Chip designed for low-power AI-IoT end-nodes fabricated in GlobalFoundries 22nm FDX. The SoC combines a cluster of 16 RISC-V DSP cores supporting specialized 2-to-4b arithmetic (XpulpNN) with