Architecture
Research
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs
Abstract
AXI-REALM is a lightweight, modular, and open-source extension to AXI4 interconnects designed to restore timing predictability and control access contention in heterogeneous real-time SoCs. Utilizing a credit-based mechanism, AXI-REALM distributes and regulates
Research
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors
Abstract
PELS (Peripheral Event Linking System) is proposed as a lightweight, flexible solution to manage peripheral interactions in ultra-low-power IoT processors without requiring continuous mediation by the main CPU. This open-source, peripheral-agnostic architecture
Research
CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers
Abstract
This work introduces CV32RT, an enhanced, open-source 32-bit RISC-V core designed to overcome the latency shortcomings of standard RISC-V interrupt handling in embedded systems. CV32RT integrates the RISC-V CLIC specification and features
Research
Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV 1.0 Compliant Open-Source Processor
Abstract
Ara2 is presented as the first fully open-source vector processor compliant with the RISC-V V 1.0 frozen ISA, demonstrating state-of-the-art energy efficiency and achieving 95% functional-unit utilization on intensive workloads. Fabricated
Research
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications
Abstract
This work introduces IndexMAC, a custom vector index-multiply-accumulate instruction proposed for RISC-V processors, designed to accelerate structured-sparse matrix multiplications (SSMM) critical to modern Machine Learning (ML) applications. IndexMAC enables low-cost indirect reads
Research
Supporting Custom Instructions with the LLVM Compiler for RISC-V Processor
Abstract
This study analyzes the process of integrating custom hardware instructions into the LLVM compiler backend for RISC-V processors, driven by the need for high-performance hardware accelerators. The authors delineate the required compiler