Architecture
Research
Algorithms for Improving the Automatically Synthesized Instruction Set of an Extensible Processor
Abstract
This paper introduces novel algorithms designed to optimize the automatically synthesized instruction sets (ISAs) used in extensible processors and hardware accelerators like RISC-V. The methods include a Common Operations Clustering algorithm to
Research
RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device
Abstract
The RHS-TRNG is a novel True Random Number Generator utilizing the stochastic switching characteristics of Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTJ) devices to deliver high-quality randomness. This design achieves exceptional speed, reaching
Research
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine
Abstract
Siracusa is a 16 nm heterogeneous RISC-V System-on-Chip designed for latency- and power-constrained Extended Reality (XR) applications requiring intensive Machine Learning. The key innovation is the tightly-coupled "At-Memory" integration of
Research
Branch Prediction in Hardcaml for a RISC-V 32im CPU
Abstract
This paper presents a hardware implementation of aggressive branch prediction techniques for a high-performance RISC-V 32im CPU core. The methodology progresses from simple static decode stage predictions to the utilization of the
Research
32-Bit RISC-V CPU Core on Logisim
Abstract
This project details the successful design and implementation of a 32-bit RISC-V CPU Core utilizing the Logisim digital logic simulation software. The effort capitalizes on the open-standard, royalty-free nature of the RISC-V
Research
Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V
Abstract
This study proposes a novel multi-level granularity Information Flow Tracking (IFT) model designed specifically for the RISC-V architecture to enhance runtime security and system integrity. The approach integrates hardware-based IFT with a