Architecture

Research

LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation

Abstract The LRSCwait paper introduces LRwait and SCwait, a novel synchronization pair designed to eliminate performance-degrading polling and retries common in traditional Load-Reserved/Store-Conditional (LRSC) operations on manycore systems. The proposed Colibri architecture

By Admin 17 Jan 2024 • 2 min read •

Research

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators (Full Report)

By Admin 10 Jan 2024 • 4 min read •

Research

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators

Abstract X-HEEP (eXtendible Heterogeneous Energy-Efficient Platform) is an open-source, configurable RISC-V microcontroller designed to natively support and accelerate the integration of custom ultra-low-power edge accelerators. The platform offers extensive customization options, including variable

By Admin 10 Jan 2024 • 2 min read •

Research

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication (Full Report)

By Admin 8 Jan 2024 • 3 min read •

Research

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication

Abstract The paper proposes Matrix eXtension (MX), a lightweight enhancement to the open-source RISC-V Vector (RVV) ISA designed to significantly boost the energy efficiency of Dense Matrix Multiplication (MatMul). MX avoids expensive dedicated

By Admin 8 Jan 2024 • 2 min read •

Research

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication

Originally published on ArXiv - Hardware Architecture Computer Science > Hardware Architecture arXiv:2401.04012v1 (cs) [Submitted on 8 Jan 2024] Title:MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient

By Admin 8 Jan 2024 • 4 min read •

Research

Floating Point HUB Adder for RISC-V Sargantana Processor (Full Report)

By Admin 8 Jan 2024 • 2 min read •

Research

Floating Point HUB Adder for RISC-V Sargantana Processor

Abstract This paper introduces a tailored Floating Point HUB Adder specifically implemented within the Sargantana RISC-V processor. The HUB format is utilized as an emerging technique to improve hardware requirements and reduce processing

By Admin 8 Jan 2024 • 1 min read •

Research

A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation (Full Report)

By Admin 7 Jan 2024 • 4 min read •

Research

A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation

Abstract The Shaheen SoC is a 9mm² heterogeneous RISC-V based processor designed to enable secure and autonomous navigation for energy-constrained nano-UAVs, addressing the need for advanced ML capabilities and secure operating system co-existence.

By Admin 7 Jan 2024 • 2 min read •

Research

TitanCFI: Toward Enforcing Control-Flow Integrity in the Root-of-Trust (Full Report)

By Admin 4 Jan 2024 • 3 min read •

Research

TitanCFI: Toward Enforcing Control-Flow Integrity in the Root-of-Trust

Abstract TitanCFI is a novel architecture designed to enforce Control-Flow Integrity (CFI) within the Root-of-Trust (RoT) on modern RISC-V platforms, mitigating attacks that divert control flow. This approach modifies the protected core'

By Admin 4 Jan 2024 • 2 min read •