Architecture

Research

Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters

Abstract This work introduces a hybrid architecture enabling efficient, reconfigurable systolic computation on shared L1-memory manycore clusters utilizing small RISC-V cores as processing elements (PEs). The innovation includes two low-overhead RISC-V ISA extensions,

By Admin 20 Feb 2024 • 2 min read •

Research

Optimization of a Line Detection Algorithm for Autonomous Vehicles on a RISC-V with Accelerator (Full Report)

By Admin 1 Feb 2024 • 3 min read •

Research

Optimization of a Line Detection Algorithm for Autonomous Vehicles on a RISC-V with Accelerator

Abstract This paper explores the optimization of a line detection algorithm critical for autonomous vehicles, addressing strict real-time and safety requirements often unmet by general-purpose processors alone. The approach utilizes a heterogeneous system

By Admin 1 Feb 2024 • 1 min read •

Research

Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs (Full Report)

By Admin 31 Jan 2024 • 3 min read •

Research

Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs

Abstract Makinote is a massive, FPGA-based hardware/software platform developed at the Barcelona Supercomputing Center for high-speed, pre-silicon emulation of complex RISC-V designs. Composed of 96 AMD/Xilinx Alveo U55c FPGAs, the cluster

By Admin 31 Jan 2024 • 2 min read •

Research

A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference (Full Report)

By Admin 30 Jan 2024 • 3 min read •

Research

A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference

Abstract This work introduces SPEED, a scalable RISC-V vector (RVV) processor architecture designed to efficiently execute multi-precision deep neural network (DNN) inference, addressing limitations in precision support and dataflow of existing RVV designs.

By Admin 30 Jan 2024 • 2 min read •

Research

TOP: Towards Open & Predictable Heterogeneous SoCs (Full Report)

By Admin 28 Jan 2024 • 3 min read •

Research

TOP: Towards Open & Predictable Heterogeneous SoCs

Abstract The TOP methodology addresses the critical challenge of ensuring predictability in heterogeneous real-time SoCs by leveraging the rise of open-source hardware (RISC-V) to facilitate comprehensive architectural analysis. This approach models and analyzes

By Admin 28 Jan 2024 • 2 min read •

Research

A RISC-V SOC for Terahertz IoT Devices: Implementation and design challenges (Full Report)

By Admin 26 Jan 2024 • 3 min read •

Research

A RISC-V SOC for Terahertz IoT Devices: Implementation and design challenges

Abstract This study addresses the critical challenge of maintaining linearity and high precision in Digital-to-Analog Converters (DACs) for prospective Terahertz (THz) IoT transceivers. The paper introduces a novel signal processing technique called Modified

By Admin 26 Jan 2024 • 2 min read •

Research

LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation (Full Report)

By Admin 17 Jan 2024 • 3 min read •