Architecture

Research

QED: Scalable Verification of Hardware Memory Consistency

Abstract QED is a novel, scalable verification methodology designed to detect complex Memory Consistency Model (MCM) bugs in out-of-order (OOO) processors, surpassing the severe scaling limits of prior bounded verification techniques. It achieves

By Admin 3 Apr 2024 • 2 min read •

Research

Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices (Full Report)

By Admin 2 Apr 2024 • 3 min read •

Research

Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices

Abstract This paper presents an open-source framework addressing the gap in RISC-V simulation tools by integrating functional instruction set simulation (ISS) with detailed extra-functional power modeling. The framework combines GVSoC for functional RISC-V

By Admin 2 Apr 2024 • 2 min read •

Research

Electron-Tunnelling-Noise Programmable Random Variate Accelerator for Monte Carlo Sampling (Full Report)

By Admin 25 Mar 2024 • 3 min read •

Research

Electron-Tunnelling-Noise Programmable Random Variate Accelerator for Monte Carlo Sampling

Abstract This article introduces an electron-tunneling-noise programmable random variate accelerator designed to drastically improve the sampling stage of Monte Carlo simulations. Integrated with a FemtoRV RISC-V soft processor using the LiteX framework on

By Admin 25 Mar 2024 • 2 min read •

Research

Analytical Heterogeneous Die-to-Die 3D Placement with Macros (Full Report)

By Admin 14 Mar 2024 • 3 min read •

Research

Analytical Heterogeneous Die-to-Die 3D Placement with Macros

Abstract This paper introduces an innovative analytical framework for 3D mixed-size placement in heterogeneous, face-to-face (F2F) bonded 3D ICs, effectively integrating large macros and standard cells. The method employs a dedicated density model,

By Admin 14 Mar 2024 • 2 min read •

Research

PUMA: Efficient and Low-Cost Memory Allocation and Alignment Support for Processing-Using-Memory Architectures (Full Report)

By Admin 7 Mar 2024 • 3 min read •

Research

PUMA: Efficient and Low-Cost Memory Allocation and Alignment Support for Processing-Using-Memory Architectures

Abstract Processing-Using-DRAM (PUD) architectures require strict data alignment, mandating that operands reside in the same DRAM subarray and are aligned to row boundaries, constraints standard OS allocators cannot meet. This paper proposes PUMA,

By Admin 7 Mar 2024 • 2 min read •

Research

SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm (Full Report)

By Admin 27 Feb 2024 • 3 min read •

Research

SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm

Abstract This paper introduces SSRESF, a Sensitivity-aware Single-particle Radiation Effects Simulation Framework designed to overcome the limitations of traditional radiation testing in large-scale System-on-Chip (SoC) designs. SSRESF utilizes the Support Vector Machine (SVM)

By Admin 27 Feb 2024 • 2 min read •

Research

Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters (Full Report)

By Admin 20 Feb 2024 • 3 min read •