Architecture

Research

xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems

Abstract xTern is a lightweight RISC-V instruction set architecture extension designed to accelerate Ternary Neural Network (TNN) inference on general-purpose edge cores. This ISA extension, complemented by optimized kernels, achieves 67% higher throughput

By Admin 29 May 2024 • 2 min read •

Research

Full-stack evaluation of Machine Learning inference workloads for RISC-V systems (Full Report)

By Admin 24 May 2024 • 3 min read •

Research

Full-stack evaluation of Machine Learning inference workloads for RISC-V systems

Abstract This study conducts a full-stack performance evaluation of diverse machine learning inference workloads on RISC-V architectures using the open-source gem5 architectural simulator. Leveraging an MLIR-based compilation toolchain, the research maps complex deep

By Admin 24 May 2024 • 2 min read •

Research

Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core (Full Report)

By Admin 20 May 2024 • 3 min read •

Research

Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core

Abstract This study employs formal verification, specifically model checking, to exhaustively evaluate the hardware reliability of the RISC-V Ibex Core against Single Event Upsets (SEUs), overcoming the coverage limitations of simulation-based fault injection.

By Admin 20 May 2024 • 2 min read •

Research

A Mess of Memory System Benchmarking, Simulation and Application Profiling (Full Report)

By Admin 16 May 2024 • 4 min read •

Research

A Mess of Memory System Benchmarking, Simulation and Application Profiling

Abstract The Memory stress (Mess) framework provides a unified, open-source solution for memory system benchmarking, accurate simulation, and application profiling using holistic bandwidth–latency curves. This benchmark characterizes a wide array of high-end

By Admin 16 May 2024 • 2 min read •

Research

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications (Full Report)

By Admin 16 May 2024 • 3 min read •

Research

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications

Abstract SentryCore is a reliable, open-source RISC-V co-processor system (mega-IP) designed for advanced, real-time control functions in safety-critical applications like automotive and robotics. It ensures reliability by using three embedded RISC-V cores operating

By Admin 16 May 2024 • 2 min read •

Research

Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC (Full Report)

By Admin 6 May 2024 • 3 min read •

Research

Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC

Abstract The paper introduces Basilisk, an optimized application-specific integrated circuit (ASIC) implementation built upon the open-source Iguana RISC-V SoC, demonstrating a highly effective open-source electronic design automation (EDA) flow. By enhancing synthesis tools

By Admin 6 May 2024 • 2 min read •

Research

PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching (Full Report)

By Admin 6 May 2024 • 3 min read •