Architecture
Research
Functional ISS-Driven Verification of Superscalar RISC-V Processors
Abstract
This paper introduces SupeRFIVe, a novel methodology designed for the time-efficient and comprehensive functional verification of complex superscalar processors. SupeRFIVe leverages an Instruction Set Simulator (ISS) as a golden reference, interfacing with
Research
Switchboard: An Open-Source Framework for Modular Simulation of Large Hardware Systems
Abstract
The Switchboard open-source framework addresses the design bottleneck of simulating massive hardware systems by proposing a modular approach based on latency-insensitive interfaces. It achieves high throughput and rapid build times by utilizing
Research
An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
Abstract
This paper introduces an open-source, FPGA-based hardware-software framework designed to streamline side-channel analysis (SCA) research on IoT-class computing platforms. The system features a RISC-V System-on-Chip (SoC) and integrates an ad-hoc debug infrastructure
Research
KWT-Tiny: RISC-V Accelerated, Embedded Keyword Spotting Transformer
Abstract
This paper presents KWT-Tiny, an aggressively quantized and retrained Keyword Transformer (KWT) model adapted for bare-metal RISC-V edge devices operating under strict 64kB RAM constraints. Model optimization reduced the size from 2.
Research
Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operations
Abstract
This work introduces a novel hardware-software co-design framework featuring specialized Instruction Set Architecture (ISA) extensions and micro-architectural optimizations to efficiently execute mixed-precision neural networks on RISC-V cores. The design includes an expanded
Research
Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC
Abstract
The Trikarenos design is a fault-tolerant, 28nm RISC-V System-on-Chip developed for demanding automotive and space applications, incorporating Error Correction Codes (ECC) and Triple-Core Lockstep (TCLS) mechanisms. This study experimentally characterizes the fabricated