Architecture
Research
Enhanced LPDDR4X PHY in 12 nm FinFET
Abstract
This paper presents an enhanced LPDDR4X Physical Layer (PHY) implemented using 12 nm FinFET technology, specifically designed to improve memory reliability and power efficiency. The key innovation is the integration of advanced
Research
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals
Abstract
This paper presents the Flip FET (FFET), a novel transistor architecture that uses 3D stacking and a fully functional wafer backside to enable dual-sided standard cell designs and signal routing. Utilizing a
Research
TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs
Abstract
This paper presents the TCDM Burst Access architecture, a software-transparent solution designed to overcome bandwidth limitations in high-core-count RISC-V Vector (RVV) clusters sharing multi-banked L1 memory (TCDM). By employing a Burst Manager
Research
CIBPU: A Conflict-Invisible Secure Branch Prediction Unit
Abstract
Traditional Secure Branch Prediction Units (SBPUs) often suffer from significant performance degradation or weak security due to visible branch conflicts and reliance on vulnerable key update mechanisms. This paper introduces CIBPU, a
Research
AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
Abstract
AraXL is a novel, ultra-wide RISC-V V vector processor designed to overcome the physical scalability limitations, such as wire dominance, found in state-of-the-art vector designs for HPC and ML applications. It achieves
Research
Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors
Abstract
This work analyzes and optimizes Structured-Sparse Matrix Multiplication (SSMM) performance for Machine Learning applications running on RISC-V Vector Processors. The authors propose and integrate a new instruction, vindexmac (vector index-multiply-accumulate), designed to