Architecture
Research
Honest to a Fault: Root-Causing Fault Attacks with Pre-Silicon RISC Pipeline Characterization
Abstract
This paper presents a comprehensive methodology for conducting and root-causing controlled fault injection attacks at the pre-silicon level, tracing fault propagation from the physical layer to the system software. The study applies
Research
When Radiation Meets Linux: Analyzing Soft Errors in Linux on COTS SoCs under Proton Irradiation
Abstract
This study analyzes the vulnerability of Linux running on Commercial Off-The-Shelf (COTS) System-on-Chips (SoCs) to radiation-induced soft errors using 20-50 MeV proton irradiation. Testing diverse architectures, including ARM Cortex-A53 (14 nm FinFET
Research
A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems
Abstract
This paper introduces the METASAT platform, a novel RISC-V multicore and GPU System-on-Chip designed as a prototype for future safety-critical space missions. The architecture integrates a space-grade NOEL-V multiprocessor with the SPARROW
Research
Enhancing software-hardware co-design for HEP by low-overhead profiling of single- and multi-threaded programs on diverse architectures with Adaptyst
Abstract
The paper introduces Adaptyst, an open-source and architecture-agnostic tool designed to enhance software-hardware co-design for complex applications like High Energy Physics (HEP). Adaptyst provides low-overhead profiling of single- and multi-threaded programs, tracing
Research
Wildcat: Educational RISC-V Microprocessors
Abstract
The paper "Wildcat" challenges the traditional 5-stage pipeline model used in computer architecture education by examining simpler RISC-V organizations for teaching and implementation. Analysis across FPGA and SkyWater130 ASIC designs
Research
Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs
Abstract
This work quantitatively evaluates Input-Output Memory Management Unit (IOMMU)-based Shared Virtual Addressing (SVA) for RISC-V embedded heterogeneous SoCs, enabling zero-copy data offloading between host and accelerator. While IO address translation introduces