Architecture

Research

Work-In-Progress: Accelerating Numpy With OpenBLAS For Open-Source RISC-V Chips

Abstract This preliminary work presents a methodology for accelerating high-level Python applications, specifically those utilizing the Numpy library, on heterogeneous RISC-V Systems-on-Chip (SoCs). The approach involves modifying the OpenBLAS library to utilize OpenMP

By Admin 21 Mar 2025 • 1 min read •

Research

Fused-Tiled Layers: Minimizing Data Movement on RISC-V SoCs with Software-Managed Caches (Full Report)

By Admin 21 Mar 2025 • 3 min read •

Research

Fused-Tiled Layers: Minimizing Data Movement on RISC-V SoCs with Software-Managed Caches

Abstract This work introduces Fused-Tiled Layers (FTL), a novel algorithm designed for the automatic fusion of tiled layers in Deep Neural Networks (DNNs) to minimize excessive data movement. FTL addresses the common issue

By Admin 21 Mar 2025 • 2 min read •

Research

MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster

Originally published on ArXiv - Hardware Architecture Computer Science > Hardware Architecture arXiv:2504.03675v1 (cs) [Submitted on 21 Mar 2025] Title:MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster

By Admin 21 Mar 2025 • 3 min read •

Research

NeCTAr: A Heterogeneous RISC-V SoC for Language Model Inference in Intel 16 (Full Report)

By Admin 18 Mar 2025 • 3 min read •

Research

NeCTAr: A Heterogeneous RISC-V SoC for Language Model Inference in Intel 16

Abstract NeCTAr (Near-Cache Transformer Accelerator) is a 16nm heterogeneous multicore RISC-V System-on-Chip (SoC) integrating near-core and near-memory accelerators optimized for efficient sparse and dense machine learning inference. The prototype chip, designed for language

By Admin 18 Mar 2025 • 2 min read •

Research

HERMES: High-Performance RISC-V Memory Hierarchy for ML Workloads (Full Report)

By Admin 17 Mar 2025 • 3 min read •

Research

HERMES: High-Performance RISC-V Memory Hierarchy for ML Workloads

Abstract HERMES proposes a high-performance memory hierarchy specifically for RISC-V architectures executing demanding ML workloads like CNNs and Transformers. The core innovation involves integrating shared L3 caches with fine-grained coherence protocols and specialized

By Admin 17 Mar 2025 • 1 min read •

Research

Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing (Full Report)

By Admin 6 Mar 2025 • 3 min read •

Research

Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing

Abstract Maestro is a RISC-V System-on-Chip featuring a unified Vector-Tensor Unit (VTU) and specialized FFT accelerators, designed for highly efficient, on-device signal processing in Wearable Ultrasound (WUS) edge computing. Fabricated in low-cost 65nm

By Admin 6 Mar 2025 • 2 min read •

Research

CRAFT: Characterizing and Root-Causing Fault Injection Threats at Pre-Silicon (Full Report)

By Admin 5 Mar 2025 • 3 min read •

Research

CRAFT: Characterizing and Root-Causing Fault Injection Threats at Pre-Silicon

Abstract CRAFT is a novel framework that utilizes pre-silicon analysis to efficiently characterize and root-cause fault injection vulnerabilities in processor designs, substantially reducing the search space for post-silicon validation. Applied to a RISC-V

By Admin 5 Mar 2025 • 2 min read •