Architecture
Research
From RISC-V Cores to Neuromorphic Arrays: A Tutorial on Building Scalable Digital Neuromorphic Processors
Abstract
This tutorial paper outlines the architectural design principles for scalable digital neuromorphic processors suitable for low-power EdgeAI applications, using the SENECA platform as a primary example. The approach starts with flexible arrays
Research
Aquas: Enhancing Domain Specialization through Holistic Hardware-Software Co-Optimization based on MLIR
Abstract
Aquas is a novel, MLIR-based holistic hardware-software co-design framework addressing the performance limitations of existing open-source RISC-V ASIP frameworks. It enhances specialization via hardware improvements like a burst DMA engine and advanced
Research
RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
Abstract
This paper introduces a novel RISC-V Custom Function Unit (CFU) accelerator designed for TinyML applications, targeting the high memory wall cost associated with Depthwise Separable Convolutions (DSCs). The architecture utilizes a fused
Research
Vorion: A RISC-V GPU with Hardware-Accelerated 3D Gaussian Rendering and Training
Abstract
Vorion is a novel RISC-V GPGPU prototype designed to provide dedicated hardware acceleration for the computationally intensive 3D Gaussian Splatting (3DGS) technique. It features a scalable architecture utilizing z-tiling and a Gaussian/
Research
Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
Abstract
This paper presents a roadmap for open-source RISC-V chiplet systems designed for high-performance computing (HPC) and artificial intelligence (AI), aiming to match the performance of proprietary architectures. The initiative introduces Occamy, the
Research
A Configurable Mixed-Precision Fused Dot Product Unit for GPGPU Tensor Computation
Abstract
This paper introduces a scalable mixed-precision fused dot product unit designed to overcome the suboptimal throughput of discrete arithmetic units in GPGPUs for Deep Learning workloads. Integrated into the open-source RISC-V Vortex