Architecture

Research

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes

Abstract WebRISC-V is a new web-based educational simulator designed to visualize the pipelined execution of 64-bit RISC-V assembly programs, adhering to the RV64IM specification. The tool allows users to inspect the internal state

By Admin 30 Mar 2025 • 1 min read •

Research

CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device (Full Report)

By Admin 28 Mar 2025 • 3 min read •

Research

CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device

Abstract CIMR-V is an end-to-end SRAM-based Computing-in-Memory (CIM) accelerator integrated with a RISC-V core designed specifically for AI edge devices. The architecture addresses the long latency associated with loading large models from DRAM

By Admin 28 Mar 2025 • 2 min read •

Research

Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors (Full Report)

By Admin 26 Mar 2025 • 3 min read •

Research

Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors

Abstract Modern accelerators relying on scalar in-order cores often suffer from pipeline stalls, an issue traditionally mitigated by loop unrolling which increases undesirable register pressure. This work introduces 'scalar chaining,' a

By Admin 26 Mar 2025 • 2 min read •

Research

Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores (Full Report)

By Admin 26 Mar 2025 • 3 min read •

Research

Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores

Abstract This paper introduces the COPIFT methodology and associated RISC-V ISA extensions to enable low-cost, flexible dual-issue execution on energy-efficient in-order cores. Designed to accelerate mixed integer and floating-point workloads common in modern

By Admin 26 Mar 2025 • 2 min read •

Research

Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6 (Full Report)

By Admin 24 Mar 2025 • 3 min read •

Research

Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6

Abstract This work presents the design and evaluation of a Processor Tracing System compliant with the RISC-V Efficient Trace specification for Instruction Branch Tracing. Integrated into the CVA6 edge architecture, the system was

By Admin 24 Mar 2025 • 1 min read •

Research

Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs (Full Report)

By Admin 21 Mar 2025 • 3 min read •

Research

Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs

Abstract The large area consumption of the Vector Register File (VRF) in RISC-V vector engines hinders their deployment in low-cost CPUs designed for edge Machine Learning acceleration. This paper introduces "Register Dispersion,

By Admin 21 Mar 2025 • 2 min read •

Research

Work-In-Progress: Accelerating Numpy With OpenBLAS For Open-Source RISC-V Chips (Full Report)

By Admin 21 Mar 2025 • 3 min read •