Architecture

Research

SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions

Abstract This paper presents SpikeStream, an optimization technique designed to accelerate Spiking Neural Network (SNN) inference on general-purpose RISC-V multicore clusters using a low-overhead ISA extension for sparse computation streaming. SpikeStream maps weight

By Admin 8 Apr 2025 • 2 min read •

Research

CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor (Full Report)

By Admin 8 Apr 2025 • 3 min read •

Research

CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor

Abstract CVA6-VMRT proposes a modular hardware extension for the open-source RISC-V CVA6 core to achieve time-predictable virtual memory, addressing a critical need in complex autonomous systems. This design incorporates dynamically partitioned Translation Look-aside

By Admin 8 Apr 2025 • 2 min read •

Research

FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors (Full Report)

By Admin 7 Apr 2025 • 3 min read •

Research

FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors

Abstract FERIVer is a novel FPGA-assisted System-on-Chip framework designed to accelerate the Register Transfer Level (RTL) verification of RISC-V processors. It resolves the traditional trade-off between speed and accuracy by leveraging an embedded

By Admin 7 Apr 2025 • 1 min read •

Research

Virtual memory for real-time systems using hPMP (Full Report)

By Admin 6 Apr 2025 • 3 min read •

Research

Virtual memory for real-time systems using hPMP

Abstract To meet stringent automotive safety and security requirements, this work proposes hPMP, an extension to the RISC-V SPMP specification designed for real-time systems. The key innovation enables virtual address redirection for selected

By Admin 6 Apr 2025 • 1 min read •

Research

ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions (Full Report)

By Admin 3 Apr 2025 • 3 min read •

Research

ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions

Abstract ARCANE introduces a novel Adaptive RISC-V Cache Architecture that transforms the traditional cache subsystem into a tightly-coupled compute-near-memory coprocessor, specifically addressing the von Neumann data movement bottleneck. This architecture allows the RISC-V

By Admin 3 Apr 2025 • 2 min read •

Research

Exploring energy consumption of AI frameworks on a 64-core RV64 Server CPU (Full Report)

By Admin 3 Apr 2025 • 3 min read •

Research

Exploring energy consumption of AI frameworks on a 64-core RV64 Server CPU

Abstract This study conducts a comprehensive energy consumption benchmark of deep learning inference models running on the 64-core SOPHON SG2042 RISC-V server CPU. The research compared leading AI frameworks, including PyTorch, ONNX Runtime,

By Admin 3 Apr 2025 • 2 min read •

Research

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes (Full Report)

By Admin 30 Mar 2025 • 3 min read •