Architecture

Research

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs

Abstract This paper proposes novel RISC-V instruction set extensions designed through hardware/software co-design to efficiently accelerate sparse Deep Neural Networks (DNNs) on FPGAs. The design introduces custom functional units: one leveraging reserved

By Admin 28 Apr 2025 • 2 min read •

Research

Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP) (Full Report)

By Admin 22 Apr 2025 • 3 min read •

Research

Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)

Abstract The Zoozve instruction extension addresses performance limitations in the standard RISC-V Vector Extension (RVV), specifically those caused by static register counts and required strip-mining for long vectors. Zoozve is a novel extension

By Admin 22 Apr 2025 • 2 min read •

Research

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture (Full Report)

By Admin 20 Apr 2025 • 3 min read •

Research

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture

Abstract CVA6S+ is an enhanced, open-source superscalar RISC-V core featuring optimized microarchitectural components like improved branch prediction and register renaming. These enhancements lead to a 43.5% performance increase over the scalar CVA6

By Admin 20 Apr 2025 • 2 min read •

Research

DataMaestro: A Versatile and Efficient Data Streaming Engine Bringing Decoupled Memory Access To Dataflow Accelerators (Full Report)

By Admin 18 Apr 2025 • 3 min read •

Research

DataMaestro: A Versatile and Efficient Data Streaming Engine Bringing Decoupled Memory Access To Dataflow Accelerators

Abstract DataMaestro is a novel data streaming engine that applies a decoupled access/execute architecture to Deep Neural Network (DNN) dataflow accelerators to mitigate performance bottlenecks caused by data movement. It features programmable

By Admin 18 Apr 2025 • 2 min read •

Research

VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformers (Full Report)

By Admin 15 Apr 2025 • 3 min read •

Research

VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformers

Abstract The VEXP project introduces a low-cost RISC-V Instruction Set Architecture (ISA) extension specifically designed to accelerate the Softmax computation bottleneck found in modern Transformer models. This is achieved by integrating a custom

By Admin 15 Apr 2025 • 2 min read •

Research

Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension (Full Report)

By Admin 15 Apr 2025 • 3 min read •

Research

Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension

Abstract This paper introduces the Unlimited Vector Processing (UVP) instruction set extension for RISC-V, specifically targeting performance improvements in wireless baseband processing (WBP). UVP overcomes conventional vector architecture constraints by implementing a novel

By Admin 15 Apr 2025 • 2 min read •

Research

AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance (Full Report)

By Admin 14 Apr 2025 • 3 min read •