Architecture

Research

Assessing Tenstorrent's RISC-V MatMul Acceleration Capabilities

Originally published on ArXiv - Hardware Architecture Computer Science > Performance arXiv:2505.06085v3 (cs) [Submitted on 9 May 2025 (v1), last revised 20 Jun 2025 (this version, v3)] Title:Assessing Tenstorrent'

By Admin 9 May 2025 • 4 min read •

Research

Taming Offload Overheads in a Massively Parallel Open-Source RISC-V MPSoC: Analysis and Optimization (Full Report)

By Admin 9 May 2025 • 3 min read •

Research

Taming Offload Overheads in a Massively Parallel Open-Source RISC-V MPSoC: Analysis and Optimization

Abstract This study analyzes and optimizes the significant synchronization and communication overheads associated with offloading fine-grained tasks in heterogeneous, massively parallel RISC-V MPSoCs, specifically using the open-source Occamy platform. Through a co-designed approach,

By Admin 9 May 2025 • 2 min read •

Research

Flexing RISC-V Instruction Subset Processors to Extreme Edge (Full Report)

By Admin 7 May 2025 • 3 min read •

Research

Flexing RISC-V Instruction Subset Processors to Extreme Edge

Abstract This paper introduces an automated methodology for creating RISC-V Instruction Subset Processors (RISSPs) specifically tailored for power and area-constrained Extreme Edge applications, including those using flexible integrated circuits (FlexICs). The approach treats

By Admin 7 May 2025 • 2 min read •

Research

Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU (Full Report)

By Admin 6 May 2025 • 3 min read •

Research

Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU

Abstract This paper investigates two approaches—hardware acceleration and pure software implementation—for incorporating modern, non-SPMD warp-level features into RISC-V GPUs, specifically using the Vortex architecture. The evaluation demonstrates that implementing these features

By Admin 6 May 2025 • 1 min read •

Research

Open Challenges for a Production-ready Cloud Environment on top of RISC-V hardware (Full Report)

By Admin 5 May 2025 • 3 min read •

Research

Open Challenges for a Production-ready Cloud Environment on top of RISC-V hardware

Abstract This article, stemming from the Vitamin-V European project, investigates the necessary steps to create a functional, production-ready cloud environment leveraging RISC-V hardware. The authors describe the creation of a prototype RISC-V cluster

By Admin 5 May 2025 • 1 min read •

Research

The Open-Source BlackParrot-BedRock Cache Coherence System (Full Report)

By Admin 2 May 2025 • 3 min read •

Research

The Open-Source BlackParrot-BedRock Cache Coherence System

Abstract This work introduces the open-source BlackParrot-BedRock (BP-BedRock) cache coherence system, built upon the novel BedRock protocol that utilizes canonical MOESIF states while eliminating complex transient states to simplify verification. The research evaluates

By Admin 2 May 2025 • 2 min read •

Research

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs (Full Report)

By Admin 28 Apr 2025 • 3 min read •