Architecture

Research

An Integrated UVM-TLM Co-Simulation Framework for RISC-V Functional Verification and Performance Evaluation (Full Report)

By Admin 15 May 2025 • 3 min read •

Research

An Integrated UVM-TLM Co-Simulation Framework for RISC-V Functional Verification and Performance Evaluation

Abstract This paper introduces an integrated UVM-TLM co-simulation framework designed to efficiently verify complex RISC-V processors by simultaneously evaluating functional correctness and performance. The methodology employs a configurable Transaction-Level Model (vmodel) of a

By Admin 15 May 2025 • 1 min read •

Research

Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS (Full Report)

By Admin 15 May 2025 • 3 min read •

Research

Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS

Abstract The Basilisk project introduces the largest end-to-end open-source system-on-chip (SoC) to date, successfully integrating a 64-bit Linux-capable RISC-V core on a 34 mm² die. Implemented in 130 nm BiCMOS technology, this effort

By Admin 15 May 2025 • 2 min read •

Research

Area Comparison of CHERIoT and PMP in Ibex (Full Report)

By Admin 13 May 2025 • 3 min read •

Research

Area Comparison of CHERIoT and PMP in Ibex

Abstract This paper analyzes the hardware area cost of implementing Physical Memory Protection (PMP) and the CHERIoT capability-based security extension within the Ibex RISC-V core. Synthesis results show that PMP (16 regions) adds

By Admin 13 May 2025 • 2 min read •

Research

e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications (Full Report)

By Admin 13 May 2025 • 3 min read •

Research

e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications

Abstract This work introduces e-GPU, an open-source and highly configurable RISC-V Graphic Processing Unit designed to deliver parallel acceleration to ultra-low-power TinyAI devices. The platform utilizes a lightweight Tiny-OpenCL framework for programming and

By Admin 13 May 2025 • 2 min read •

Research

Efficient Implementation of RISC-V Vector Permutation Instructions (Full Report)

By Admin 11 May 2025 • 3 min read •

Research

Efficient Implementation of RISC-V Vector Permutation Instructions

Abstract The efficient hardware implementation of RISC-V Vector (RVV) permutation instructions is complicated by their diverse control mechanisms, despite their necessity for accelerating data-parallel workloads like cryptography. This paper proposes a unified microarchitecture

By Admin 11 May 2025 • 2 min read •

Research

Assessing Tenstorrent's RISC-V MatMul Acceleration Capabilities (Full Report)

By Admin 9 May 2025 • 3 min read •

Research

Assessing Tenstorrent's RISC-V MatMul Acceleration Capabilities

Abstract This paper evaluates the performance and energy efficiency of the Tenstorrent Grayskull e75 RISC-V accelerator when executing fundamental MatMul operations critical for Large Language Models. Researchers conducted a detailed characterization of the

By Admin 9 May 2025 • 1 min read •