Architecture

Research

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm

Abstract FREESS is a new free, interactive educational simulator designed to teach instruction-level parallelism in advanced computer architecture courses. It models a RISC-V-inspired superscalar processor utilizing an extended Tomasulo's algorithm for

By Admin 9 Jun 2025 • 1 min read •

Research

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm

Originally published on ArXiv - Hardware Architecture Computer Science > Hardware Architecture arXiv:2506.07665v1 (cs) [Submitted on 9 Jun 2025] Title:FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on

By Admin 9 Jun 2025 • 4 min read •

Research

ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors (Full Report)

By Admin 7 Jun 2025 • 3 min read •

Research

ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors

Abstract ASPO (Constraint-Aware Bayesian Optimization) is a novel approach designed to efficiently tune parameters for complex FPGA-based soft processors, overcoming limitations of standard Bayesian Optimization concerning categorical constraints and lengthy optimization times. The

By Admin 7 Jun 2025 • 2 min read •

Research

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing (Full Report)

By Admin 7 Jun 2025 • 3 min read •

Research

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing

Abstract This paper analyzes the performance of a custom RISC-V SoC implementation, utilizing the RV32I base ISA with M and A extensions, specifically targeting edge computing applications. Through cycle-accurate simulation, the pipelined design

By Admin 7 Jun 2025 • 1 min read •

Research

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution (Full Report)

By Admin 30 May 2025 • 4 min read •

Research

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution

Abstract This work standardizes the proprietary XuanTie C910 Out-of-Order (OoO) RISC-V core for full compliance and introduces CVA6S+, an enhanced dual-issue version of the CVA6 core, achieving a 34.4% performance boost. A

By Admin 30 May 2025 • 2 min read •

Research

Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing (Full Report)

By Admin 25 May 2025 • 3 min read •

Research

Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing

Abstract This paper presents a novel, unified hardware solution for integrating lightweight and precision-scalable Posit arithmetic into RISC-V Floating Point Units (FPU), while maintaining compatibility with IEEE-754 standards. The implementation uses dedicated posit

By Admin 25 May 2025 • 2 min read •

Research

Modular SAIL: dream or reality? (Full Report)

By Admin 22 May 2025 • 3 min read •

Research

Modular SAIL: dream or reality?

Abstract This paper addresses the critical challenge of compositionality in the RISC-V development flow, which is necessary to fully leverage the modular nature of the ISA specification. The authors introduce "modular SAIL,

By Admin 22 May 2025 • 2 min read •