ACM
Research
Toward Comprehensive Design Space Exploration on Heterogeneous Multi-core Processors
Abstract
Designing optimal heterogeneous multi-core processors requires navigating an exponentially large Design Space Exploration (DSE) covering core mixes, interconnects, and scheduling policies. This paper introduces a novel, comprehensive DSE framework specifically tailored for
Research
TEMpesT: Testing Empirically for Memory Transistency
Abstract
TEMpesT is a novel empirical testing methodology designed to rigorously verify memory transistency behaviors in modern CPU implementations, specifically targeting the complexities of the RISC-V Weak Memory Ordering (RVWMO) model. The system
Research
Efficient Flexible Edge Inference for Mixed-Precision Quantized DNN using Customized RISC-V Core
Abstract
This paper presents a customized RISC-V core architecture specifically designed for highly efficient and flexible edge inference of mixed-precision quantized Deep Neural Networks (DNNs). The core utilizes specialized instruction set extensions and
Research
A Survey of Machine Learning Approaches in Logic Synthesis
Abstract
This survey provides a comprehensive review of the rapidly evolving landscape concerning the integration of Machine Learning (ML) techniques into classical Logic Synthesis workflows. It systematically categorizes various ML applications—ranging from
Research
svc-hook: hooking system calls on ARM64 by binary rewriting
Abstract
The paper introduces "svc-hook," a novel framework designed for intercepting and hooking system calls specifically on the ARM64 architecture. This highly effective instrumentation is achieved through the use of aggressive
Research
Recipe: Hardware-Accelerated Replication Protocols
Originally published on ACM Digital Library
Middleware '25: Proceedings of the 26th International Middleware Conference, Page 1-15.