Research

TEMpesT: Testing Empirically for Memory Transistency

Abstract TEMpesT is a novel empirical testing methodology designed to rigorously verify memory transistency behaviors in modern CPU implementations, specifically targeting the complexities of the RISC-V Weak Memory Ordering (RVWMO) model. The system

By Admin 16 Dec 2025 • 2 min read •

Research

Efficient Flexible Edge Inference for Mixed-Precision Quantized DNN using Customized RISC-V Core

Abstract This paper presents a customized RISC-V core architecture specifically designed for highly efficient and flexible edge inference of mixed-precision quantized Deep Neural Networks (DNNs). The core utilizes specialized instruction set extensions and

By Admin 16 Dec 2025 • 2 min read •

Research

Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor

Abstract This paper presents a pipeline stage resolved timing characterization framework to systematically compare a 32-bit RISC-V processor implemented on a 20 nm FPGA and a 7 nm FinFET ASIC. The analysis demonstrates

By Admin 15 Dec 2025 • 2 min read •

Research

Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing

Abstract Lyra is a novel heterogeneous RISC-V verification framework that pairs hardware acceleration via an FPGA SoC with an ISA-aware generative model, LyraGen, for processor fuzzing. This methodology enables high-throughput differential checking and

By Admin 15 Dec 2025 • 2 min read •

Research

Reproducibility and Standardization in gem5 Resources v25.0

Abstract This paper introduces significant improvements in gem5 and gem5 Resources v25.0 to address critical challenges in simulation reproducibility and standardization within computer architecture research. Key innovations include standardizing disk image creation

By Admin 15 Dec 2025 • 2 min read •

Research

A Survey of Machine Learning Approaches in Logic Synthesis

Abstract This survey provides a comprehensive review of the rapidly evolving landscape concerning the integration of Machine Learning (ML) techniques into classical Logic Synthesis workflows. It systematically categorizes various ML applications—ranging from

By Admin 15 Dec 2025 • 2 min read •

News

Qualcomm sharpens RISC-V influence with Ventana acquisition - DIGITIMES Asia

Originally published on Google News - RISC-V Qualcomm sharpens RISC-V influence with Ventana acquisition  DIGITIMES Asia

By Admin 15 Dec 2025 •

News

Qualcomm sharpens RISC-V influence with Ventana acquisition - digitimes

Originally published on Google News - RISC-V Qualcomm sharpens RISC-V influence with Ventana acquisition  digitimes

By Admin 15 Dec 2025 •

News

India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V CPU - TechPowerUp

Abstract India has launched DHRUV64, a major step in its indigenous semiconductor development, introducing the country's first 64-bit dual-core processor based on the open-source RISC-V architecture. This CPU operates at 1

By Admin 15 Dec 2025 • 1 min read •

Research

svc-hook: hooking system calls on ARM64 by binary rewriting

Abstract The paper introduces "svc-hook," a novel framework designed for intercepting and hooking system calls specifically on the ARM64 architecture. This highly effective instrumentation is achieved through the use of aggressive

By Admin 15 Dec 2025 • 2 min read •

Research

Recipe: Hardware-Accelerated Replication Protocols

Originally published on ACM Digital Library Middleware '25: Proceedings of the 26th International Middleware Conference, Page 1-15.

By Admin 15 Dec 2025 •

Research

IM-PIR: In-Memory Private Information Retrieval

Abstract IM-PIR introduces a novel architectural approach for Private Information Retrieval (PIR) by integrating the computationally intensive cryptographic operations directly into the memory subsystem, effectively addressing the data movement bottleneck known as the

By Admin 15 Dec 2025 • 2 min read •